{"title":"Memristor-Emulating-Integrate-and-Fire Neuron-Based Fully Neuromorphic Framework for Pattern Recognition","authors":"Prashant Kumar;Rajeev Kumar Ranjan;Sung-Mo Kang","doi":"10.1109/TCSII.2024.3439687","DOIUrl":null,"url":null,"abstract":"The need for low-power, area-efficient, and low-complexity hardware architectures has become an essential axis of emerging neuromorphic frameworks. Moreover, in the prevailing architectures for implementing the neural algorithms, the synaptic weights are digitally stored, which is a major Von-Neumann bottleneck in terms of energy and area. We thus introduce, for the first time, an area-efficient Memristor-Emulating-Integrate-and-Fire (MEIF) neuron-based fully neuromorphic architecture for pattern recognition. This pattern recognition scheme is based on the MEIF neuron circuit that has significantly less hardware complexity. The simulation results are based on a 1.8 V, 180-nm CMOS technology. Simulation-based experimental results show that our neuromorphic system, comprising 48 neurons, has the recognition capability with an average energy consumption of \n<inline-formula> <tex-math>$\\approx 5.255$ </tex-math></inline-formula>\n pJ per neuron for the 4X3 pixel patterns.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 12","pages":"5024-5028"},"PeriodicalIF":4.9000,"publicationDate":"2024-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Circuits and Systems II: Express Briefs","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10628115/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
The need for low-power, area-efficient, and low-complexity hardware architectures has become an essential axis of emerging neuromorphic frameworks. Moreover, in the prevailing architectures for implementing the neural algorithms, the synaptic weights are digitally stored, which is a major Von-Neumann bottleneck in terms of energy and area. We thus introduce, for the first time, an area-efficient Memristor-Emulating-Integrate-and-Fire (MEIF) neuron-based fully neuromorphic architecture for pattern recognition. This pattern recognition scheme is based on the MEIF neuron circuit that has significantly less hardware complexity. The simulation results are based on a 1.8 V, 180-nm CMOS technology. Simulation-based experimental results show that our neuromorphic system, comprising 48 neurons, has the recognition capability with an average energy consumption of
$\approx 5.255$
pJ per neuron for the 4X3 pixel patterns.
期刊介绍:
TCAS II publishes brief papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes:
Circuits: Analog, Digital and Mixed Signal Circuits and Systems
Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic
Circuits and Systems, Power Electronics and Systems
Software for Analog-and-Logic Circuits and Systems
Control aspects of Circuits and Systems.