A 102-Gb/s/lane 1.4-Vppd Linear Range PAM-8 Receiver Frontend With Multi-Path Continuous-Time Linear Equalization in 28-nm CMOS

Abstract

This brief proposes a 102-Gb/s eight-level pulse amplitude modulation (PAM-8) wireline receiver frontend system with high linearity. The receiver adopts a strategy wherein the differential signal undergoes division in the analog domain before equalization. The bias shifters control the common-mode voltage of the input signal to provide distinct dynamic regions for multiple equalizer pathways. The bias shifter circuits employing passive devices ensure both power saving and full linearity. The proposed PAM-8 receiver frontend operates at 102 Gb/s with an efficiency of 1.61 pJ/b and a linear input range of 1.4-Vppd in 28-nm CMOS.