M-HLS: Malevolent High-Level Synthesis for Watermarked Hardware IPs

Abstract

Hardware Trojan insertion in high-level synthesis (HLS) generated intellectual property (IP) designs can pose strong security concern for the designers. Backdoor hardware Trojans can be inserted in the HLS design flow to compromise the produced register transfer level (RTL) IP design. This letter presents a novel malevolent HLS (M-HLS) framework introducing the possibility of two different hardware Trojan insertion [i.e., performance degradation hardware Trojan (PD-HT) and Denial of Service hardware Trojan (DoS-HT)] in multiplexer (mux)-based interconnect stage of HLS generated watermarked IP design. The proposed framework is validated on the watermarked MESA Horner Bezier’s IP, which indicates strong performance degradation and DoS achievable by an attacker at minimal area and power overhead.