High-Performance Error and Erasure Decoding With Low Complexities Using SPC-RS Concatenated Codes

IF 3.1 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-08-06 DOI:10.1109/TVLSI.2024.3435773

Zhihao Zhou;Wei Zhang;Xinyi Guo;Jianhan Zhao;Yanyan Liu

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Abstract

In this brief, a novel single parity check-assisted error and erasure decoding (SPC-EED) algorithm over the compound channel is proposed for Reed-Solomon (RS) codes. EED is applied to the scheme of SPC-RS concatenation code. The proposed algorithm can correct most random errors with the assistance of SPC codes. Through using channel soft information, the symbols with burst errors can be identified accurately and efficiently for erasures in EED. Simulation results show that the SPC-EED algorithm can achieve coding gains of up to 0.1, 0.4, and 2.1 dB compared with burst-error correcting (BC)-SPC-ordered statistic decoding (OSD), BC-OSD, and BCHDD-low-complexity chase (LCC) for RS(255, 239) codes, respectively, at symbol error rate (SER) = 10−3. The proposed algorithm has lower computational complexities while maintaining better decoding performance. The hardware design of the SPC-threshold check module is provided. The implementation results in ASIC show that compared with the BCHDD-LCC decoder, the SPC-EED decoder improves area efficiency by 249.37% with higher energy efficiency.

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利用 SPC-RS 连接编码实现低复杂度的高性能纠错和擦除解码

本文提出了一种基于复合信道的单奇偶校验辅助错误和擦除译码（SPC-EED）算法。将EED应用于SPC-RS级联码方案。该算法可以在SPC码的辅助下对大多数随机误差进行校正。通过利用信道软信息，可以准确有效地识别突发错误的符号，并在瞬态编码中进行擦除。仿真结果表明，在符号错误率(SER) = 10−3的情况下，与突发纠错(BC)- spc -有序统计解码（OSD）、BC-OSD和bchdd -低复杂度追踪（LCC）算法相比，SPC-EED算法在RS（255, 239）码的编码增益分别可达0.1、0.4和2.1 dB。该算法在保持较好的译码性能的同时，具有较低的计算复杂度。给出了spc阈值检测模块的硬件设计。在ASIC上的实现结果表明，与BCHDD-LCC译码器相比，SPC-EED译码器的面积效率提高了249.37%，且具有更高的能量效率。

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来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.