RosebudVirt: A High-Performance and Partially Reconfigurable FPGA Virtualization Framework for Multitenant Networks

IF 2.8 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-08-07 DOI:10.1109/TVLSI.2024.3436017

Yiwei Chang;Zhichuan Guo

引用次数: 0

Abstract

Field-programmable gate arrays (FPGAs) are key accelerators in cloud data centers due to their parallelism and programmability. However, challenges such as low hardware utilization and high virtualization overhead persist. This brief presents RosebudVirt, a high-performance and partially reconfigurable FPGA virtualization framework tailored for multitenant networks. It enhances the original Rosebud by introducing single-root I/O virtualization (SR-IOV) support, partitioning the PCIe-attached FPGA device into multiple physical functions (PFs) and virtual functions (VFs) accessible to the linux kernel via PF and VF drivers. This facilitates direct mapping among tenants, VFs, and reconfigurable packet-processing units (RPUs) within the FPGA. RosebudVirt achieves near-native throughput with <1% area overhead and increases hardware utilization by up to 7.6 times by additional VF drivers and network interfaces. What is more, RosebudVirt is compatible with Kubernetes and Docker.

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

RosebudVirt：面向多租户网络的高性能和部分可重构 FPGA 虚拟化框架

现场可编程门阵列（fpga）由于其并行性和可编程性而成为云数据中心的关键加速器。然而，低硬件利用率和高虚拟化开销等挑战仍然存在。本文介绍了RosebudVirt，这是一个为多租户网络量身定制的高性能和部分可重构FPGA虚拟化框架。它通过引入单根I/O虚拟化（SR-IOV）支持来增强原来的Rosebud，将pcie连接的FPGA设备划分为多个物理功能（PF）和虚拟功能（VF）， linux内核可以通过PF和VF驱动程序访问它们。这有助于在FPGA内的租户、vf和可重新配置的分组处理单元（rpu）之间进行直接映射。RosebudVirt以<1%的面积开销实现了接近本机的吞吐量，并通过额外的VF驱动程序和网络接口将硬件利用率提高了7.6倍。更重要的是，RosebudVirt与Kubernetes和Docker兼容。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文去求助

来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.

期刊最新文献

Table of Contents IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information Table of Contents IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information