Jun Ye;Weiye Mo;Xuan Xiao;Haonan Liu;Yang Song;Wei Huang;Debin Zhang;Liang Li;Hongping Ma;Qingchun Jon Zhang;D. W. Zhang
{"title":"Wider SOA SGT MOSFET With Self-Adjusting Negative Feedback by Patterning the Varied Resistance of Source","authors":"Jun Ye;Weiye Mo;Xuan Xiao;Haonan Liu;Yang Song;Wei Huang;Debin Zhang;Liang Li;Hongping Ma;Qingchun Jon Zhang;D. W. Zhang","doi":"10.1109/LED.2024.3441235","DOIUrl":null,"url":null,"abstract":"VRS-SGT (Varied Resistance of Source Split Gate Trench MOSFETs) with self-adjusting negative feedback to balance the electrical and temperature characteristics, employing the varied resistance of patterned source is firstly developed in this letter to improve safe operating area (SOA) for automotive power devices used in linear mode. When operating in the linear mode, the max \n<inline-formula> <tex-math>${I}_{d}$ </tex-math></inline-formula>\n of VRS-SGT raises to 20 A in condition of \n<inline-formula> <tex-math>${V}_{d} = $ </tex-math></inline-formula>\n \n<inline-formula> <tex-math>${V}_{g} = 10$ </tex-math></inline-formula>\n V and \n<italic>PT</i>\n = 10 ms, increased by 48% compared with Conventional-SGT (C-SGT) due to lower ZTC and weaker positive current-temperature feedback. In addition, the low doping N-region for source resistance helps the VRS-SGT set up the self-ballast negative feedback mechanism to increase the source potential (\n<inline-formula> <tex-math>${V}_{s}$ </tex-math></inline-formula>\n), which can further suppress the trigger of parasitic NPN while slowing down the startup of MOSFETs. Varied \n<inline-formula> <tex-math>${R}_{s}$ </tex-math></inline-formula>\n in N-region can adjust the current distribution within the chip so that the temperature tends to be more uniform when operating in linear mode. In addition, the \n<inline-formula> <tex-math>${R}_{\\textit {ds}-\\textit {on}} $ </tex-math></inline-formula>\n of VRS-SGT increases by only 3%, achieving a good trade-off between SOA and \n<inline-formula> <tex-math>${R}_{\\textit {ds}-\\textit {on}}$ </tex-math></inline-formula>\n.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":null,"pages":null},"PeriodicalIF":4.1000,"publicationDate":"2024-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Electron Device Letters","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10632109/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
VRS-SGT (Varied Resistance of Source Split Gate Trench MOSFETs) with self-adjusting negative feedback to balance the electrical and temperature characteristics, employing the varied resistance of patterned source is firstly developed in this letter to improve safe operating area (SOA) for automotive power devices used in linear mode. When operating in the linear mode, the max
${I}_{d}$
of VRS-SGT raises to 20 A in condition of
${V}_{d} = $ ${V}_{g} = 10$
V and
PT
= 10 ms, increased by 48% compared with Conventional-SGT (C-SGT) due to lower ZTC and weaker positive current-temperature feedback. In addition, the low doping N-region for source resistance helps the VRS-SGT set up the self-ballast negative feedback mechanism to increase the source potential (
${V}_{s}$
), which can further suppress the trigger of parasitic NPN while slowing down the startup of MOSFETs. Varied
${R}_{s}$
in N-region can adjust the current distribution within the chip so that the temperature tends to be more uniform when operating in linear mode. In addition, the
${R}_{\textit {ds}-\textit {on}} $
of VRS-SGT increases by only 3%, achieving a good trade-off between SOA and
${R}_{\textit {ds}-\textit {on}}$
.
期刊介绍:
IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanoelectronics, optoelectronics, photovoltaics, power ICs and micro-sensors.