An improved derivative‐based phase‐locked loop for single‐phase grid synchronization under abnormal grid conditions

IF 1.8 3区 工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC International Journal of Circuit Theory and Applications Pub Date : 2024-08-07 DOI:10.1002/cta.4211
Faridul Hassan, Alok Kumar Dubey, Amritesh Kumar, Avadh Pati
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Abstract

SummaryGenerating a quadrature signal in a single‐phase system using a second‐order generalized integrator (SOGI) requires accurate frequency information. The standard SOGI phase‐locked loop (PLL) includes frequency feedback to the SOGI. However, during grid abnormalities such as voltage sag/swell and phase angle jumps, the SOGI‐PLL faces frequency disturbances that propagate to the phase detector (PD) and affects the quadrature signal generator (QSG). Furthermore, the SOGI‐PLL having two loops dependent on each other creates loop coupling phenomena; either a change in phase or frequency affects each other. SOGI‐PLL is tuning sensitive, as the SOGI block has a gain that needs to be adjusted, increases the complexity, and affects the performance of the system. There is a trade‐off between SOGI gain and PLL parameters that needs to be considered for adequate parameter design to provide accurate grid synchronization while maintaining the stability of the system. To attain better performance, researchers have proposed derivative‐based PLL (DPLL). The conventional DPLL faces challenges to noise and harmonics amplification. This paper presents an improved DPLL for single‐phase grid synchronization under adverse grid conditions. The improved derivative‐based PLL (IDPLL) comprises two improved derivative‐based quadrature signal generator (IDQSG) blocks to extract the phase‐error information for accurately estimating phase and frequency. The detailed mathematical modeling and bode plot for the IDQSG and IDPLL are presented. The proposed IDQSG eliminates the requirement of gain tuning, hence reducing complexity. Moreover, there is no interdependent loop in the IDPLL, which significantly improves the dynamic performance. A hardware setup is developed to evaluate the performance of the system in real‐time. The experimental results are obtained using an field programmable gate array (FPGA)‐based controller.
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基于导数的改进型锁相环,用于异常电网条件下的单相电网同步
摘要使用二阶广义积分器(SOGI)在单相系统中生成正交信号需要精确的频率信息。标准 SOGI 锁相环 (PLL) 包括对 SOGI 的频率反馈。然而,在出现电压下陷/波动和相角跳变等电网异常时,SOGI-PLL 会面临频率干扰,这些干扰会传播到相位检测器 (PD),并影响正交信号发生器 (QSG)。此外,SOGI-PLL 有两个相互依赖的环路,会产生环路耦合现象;相位或频率的变化会相互影响。SOGI-PLL 对调谐很敏感,因为 SOGI 块的增益需要调整,这增加了系统的复杂性,并影响系统的性能。SOGI 增益和 PLL 参数之间存在权衡,需要考虑适当的参数设计,以提供精确的电网同步,同时保持系统的稳定性。为了获得更好的性能,研究人员提出了基于导数的 PLL(DPLL)。传统的 DPLL 面临着噪声和谐波放大的挑战。本文提出了一种改进型 DPLL,用于在不利电网条件下实现单相电网同步。改进型导数式 PLL(IDPLL)包括两个改进型导数式正交信号发生器(IDQSG)模块,用于提取相位误差信息,以准确估计相位和频率。本文介绍了 IDQSG 和 IDPLL 的详细数学建模和博德图。所提出的 IDQSG 消除了增益调整的要求,从而降低了复杂性。此外,IDPLL 中不存在相互依赖的环路,从而大大提高了动态性能。为评估系统的实时性能,开发了一个硬件装置。实验结果是使用基于现场可编程门阵列 (FPGA) 的控制器获得的。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
International Journal of Circuit Theory and Applications
International Journal of Circuit Theory and Applications 工程技术-工程:电子与电气
CiteScore
3.60
自引率
34.80%
发文量
277
审稿时长
4.5 months
期刊介绍: The scope of the Journal comprises all aspects of the theory and design of analog and digital circuits together with the application of the ideas and techniques of circuit theory in other fields of science and engineering. Examples of the areas covered include: Fundamental Circuit Theory together with its mathematical and computational aspects; Circuit modeling of devices; Synthesis and design of filters and active circuits; Neural networks; Nonlinear and chaotic circuits; Signal processing and VLSI; Distributed, switched and digital circuits; Power electronics; Solid state devices. Contributions to CAD and simulation are welcome.
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