Bhaskar, DR, Shrivastava, M, Raj, A, Kumar, P. Floating Parallel Lossy Inductance, Parallel Lossy Capacitance, Parallel C-D, and Lossless Capacitance Multiplier Circuits Using Current Feedback Operational Amplifiers. Int J Circ Theor Appl. 2024; 52(3): 1489–1517, https://doi.org/10.1002/cta.3828.
The following corrections should be incorporated in Appendix A of the above article:
This letter presents preliminary results on the evolution and application of a technique of infusing linear electronic tunability in CMOS OTA-C oscillators which involves a translinear squarer in the bias circuit of the OTA thereby making its transconductance a linear function of the external DC bias current.
This paper presents two third-order active-RC quadrature sinusoidal oscillator configurations incorporating the operational amplifier (op-amp) with a minimal number of passive components. The proposed designs employ an inverting integrator followed by a two-stage RC phase-shift network, forming a feedback loop that satisfies the Barkhausen criterion for sustained oscillation. The circuits generate two sinusoidal outputs with a 90° phase difference. One of the designs incorporates just a single op-amp. Theoretical analyses are provided to derive the frequency and condition of oscillations. Experimental results confirm the validity of the designs and demonstrate good agreement with the analytical predictions. Because of their simplicity and low component count, the proposed oscillators are particularly suitable for integrated circuit implementation in communication and signal processing systems.
This short communication presents approximate solutions for a nonlinear diode circuit followed by an RC shunt filter. The diode's exponential current–voltage characteristic introduces strong nonlinearity, making the analysis challenging. By applying the Lambert W function, closed-form approximations of the circuit voltages and currents are derived. These expressions are further enhanced through a g-function-based approach to overcome the numerical limitations of the Lambert W evaluation. The proposed model is validated through MATLAB/SIMSCAPE and PSIM simulations, and further assessed using high-fidelity software simulations within the Typhoon HIL environment, demonstrating excellent consistency with the reference results. Furthermore, the impact of different diode modeling approaches on the output voltage waveforms is systematically analyzed, revealing a pronounced influence on both amplitude and transient behavior. The presented method thus offers an accurate, computationally efficient, and experimentally confirmed analytical tool for the modeling of nonlinear diode–RC circuits.
This paper presents a novel analog predistortion (APD) design based on a single linearizing branch. The APD architecture design consists of a branch line coupler connected to a T-junction and a single linearizing branch with a single PIN diode. The analytical equations for gain and phase conversions of the proposed APD structure are derived using even- and odd-mode analysis. The design procedure of the proposed APD to compensate power amplifiers (PAs) for certain AM/AM and AM/PM is presented. Simulation and measurement results verify the performance of the proposed APD. The measurement results of the proposed APD achieve a 5.3-dB conversion gain and 10° phase compression centered at 1 GHz with 9% fractional bandwidth. To our knowledge, this is the first matched reflective-type APD that utilizes a single linearizing branch to simplify, compact, and reduce the power consumption of the APD structure. Furthermore, a 500-W PA is linearized using the proposed APD. The measurements indicate that the APD shifts the 1-dB compression point by 3.8 dB, and the phase change is reduced to less than 1.8°, whereas the IM3 is improved by 12 dB at 3-dB output power backoff.
The diode–series–parallel resistance circuit, which includes both series and shunt (parasitic) resistances, represents a generalized framework for diode-based electrical models with broad applicability in electronics and power engineering. This paper presents analytical and approximate solutions for this circuit, utilizing the g-function. To the best of our knowledge, this is the first application of the g-function to the generalized diode–series–parallel resistance circuit, extending its usability beyond solar cell configurations. Furthermore, the approximate solutions are derived through Halley's iterative procedure and Newton's method, offering an efficient and systematic approach to solving such nonlinear systems. By comparing the proposed solutions with existing literature and validating them through MATLAB/SIMSCAPE simulations as well as experimental measurements conducted in the laboratory, the results underscore the effectiveness and applicability of the proposed techniques. These findings provide valuable insights into the accurate and robust modeling of the generalized diode–series–parallel resistance circuit.
For islanded AC-DC hybrid microgrids with limited communication resources, this paper proposes a distributed secondary optimal power control strategy based on a dynamic event-triggered mechanism. By introducing incremental costs associated with powers, distributed secondary frequency control in AC subnet and distributed secondary voltage control in DC subnet are designed to ensure the restoration of frequency and voltage to the references, and the optimal power sharing. Moreover, the communication frequency between distributed generators is reduced by triggered communication, which is determined by the preset dynamic triggered thresholds. By using Lyapunov stability theory, this paper rigorously proves the stability of the control system. Finally, simulations results verify the effectiveness of the designed control strategy.
This work presents a novel approach to broadband proximity-coupled millimeter-wave microstrip array design based on a substrate integrated waveguide (SIW) feeding network, tailored specifically to automotive radar applications. The antenna array includes a central microstrip line with a series of indirectly adjacent parasitic coupled trapezoidal patches periodically arranged on both sides. By precisely adjusting the gap between these parasitic patches and lines to control the normalized impedance of the radiating elements, it helps to achieve broadband and low sidelobe levels (SLLs) characteristics. To validate the proposed design, two antennas—a 1 × 16 linear array and an 8 × 16 planar array based on the SIW feeding network—are developed to operate within the 77- to 81-GHz range. The measured SLLs are lower than −20 dB, with measured gains exceeding 15 dBi for the 1 × 16 array and 20 dBi for the 8 × 16 array across the 77- to 81-GHz band. The impedance bandwidth of the 8 × 16 planar array reaches 6.8% (76.2 GHz–81.5 GHz).
The letter concerns a clamped-type magnetic energy harvester (MEH) equipped with an AC-side series-connected capacitor, powering a constant-voltage-type load (CVL) via a diode rectifier. It was recently shown that introducing a series-connected capacitor to a passive MEH enlarges harvested power due to the possibility of increasing the load voltage without aggregating the amount of volt-seconds applied to the core. Yet, the capacitance value needs to be primary current dependent. This brief provides analytical guidelines for designing an AC-side capacitor-equipped MEH for driving a given CVL with maximum attainable power. Experimental results of a MEH capable of harvesting 310 W from a conductor carrying 350 ARMS, 50 Hz current while driving a 70 V CVL are given to validate the proposed design process.
Trial Registration: Irrelevant
The transition from idealized memristor models to physical implementations, such as resistive random access memory (RRAM) devices, is pivotal for advancing neuromorphic circuits in hardware. However, real-world RRAM devices face challenges due to inherent variability and fabrication tolerances, which hinder their adoption. This study presents the variability intensity model (VIM), a statistical framework designed to assess variability in RRAM devices. The VIM is employed to evaluate the resilience of a memristor-based Hindmarsh–Rose circuit, which models neuronal behavior in biological systems. The results indicate that the circuit exhibits heightened sensitivity to variability in high-conductance states, while demonstrating increased tolerance in low-conductance states. This observation is consistent with RRAM characteristics, where conductance variability decreases as conductance increases. Furthermore, robust spiking dynamics are observed, though the bursting behavior remains sensitive, leading to critical parameter constraints for RRAM devices. By employing a variability model based on real-world measurements, this work establishes a crucial foundation for the implementation of memristor-based Hindmarsh–Rose circuits in hardware, where variability is a paramount consideration.
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：