International Journal of Circuit Theory and Applications最新文献

This paper presents a novel analog predistortion (APD) design based on a single linearizing branch. The APD architecture design consists of a branch line coupler connected to a T-junction and a single linearizing branch with a single PIN diode. The analytical equations for gain and phase conversions of the proposed APD structure are derived using even- and odd-mode analysis. The design procedure of the proposed APD to compensate power amplifiers (PAs) for certain AM/AM and AM/PM is presented. Simulation and measurement results verify the performance of the proposed APD. The measurement results of the proposed APD achieve a 5.3-dB conversion gain and 10° phase compression centered at 1 GHz with 9% fractional bandwidth. To our knowledge, this is the first matched reflective-type APD that utilizes a single linearizing branch to simplify, compact, and reduce the power consumption of the APD structure. Furthermore, a 500-W PA is linearized using the proposed APD. The measurements indicate that the APD shifts the 1-dB compression point by 3.8 dB, and the phase change is reduced to less than 1.8°, whereas the IM3 is improved by 12 dB at 3-dB output power backoff.

The diode–series–parallel resistance circuit, which includes both series and shunt (parasitic) resistances, represents a generalized framework for diode-based electrical models with broad applicability in electronics and power engineering. This paper presents analytical and approximate solutions for this circuit, utilizing the g-function. To the best of our knowledge, this is the first application of the g-function to the generalized diode–series–parallel resistance circuit, extending its usability beyond solar cell configurations. Furthermore, the approximate solutions are derived through Halley's iterative procedure and Newton's method, offering an efficient and systematic approach to solving such nonlinear systems. By comparing the proposed solutions with existing literature and validating them through MATLAB/SIMSCAPE simulations as well as experimental measurements conducted in the laboratory, the results underscore the effectiveness and applicability of the proposed techniques. These findings provide valuable insights into the accurate and robust modeling of the generalized diode–series–parallel resistance circuit.

For islanded AC-DC hybrid microgrids with limited communication resources, this paper proposes a distributed secondary optimal power control strategy based on a dynamic event-triggered mechanism. By introducing incremental costs associated with powers, distributed secondary frequency control in AC subnet and distributed secondary voltage control in DC subnet are designed to ensure the restoration of frequency and voltage to the references, and the optimal power sharing. Moreover, the communication frequency between distributed generators is reduced by triggered communication, which is determined by the preset dynamic triggered thresholds. By using Lyapunov stability theory, this paper rigorously proves the stability of the control system. Finally, simulations results verify the effectiveness of the designed control strategy.

This work presents a novel approach to broadband proximity-coupled millimeter-wave microstrip array design based on a substrate integrated waveguide (SIW) feeding network, tailored specifically to automotive radar applications. The antenna array includes a central microstrip line with a series of indirectly adjacent parasitic coupled trapezoidal patches periodically arranged on both sides. By precisely adjusting the gap between these parasitic patches and lines to control the normalized impedance of the radiating elements, it helps to achieve broadband and low sidelobe levels (SLLs) characteristics. To validate the proposed design, two antennas—a 1 × 16 linear array and an 8 × 16 planar array based on the SIW feeding network—are developed to operate within the 77- to 81-GHz range. The measured SLLs are lower than −20 dB, with measured gains exceeding 15 dBi for the 1 × 16 array and 20 dBi for the 8 × 16 array across the 77- to 81-GHz band. The impedance bandwidth of the 8 × 16 planar array reaches 6.8% (76.2 GHz–81.5 GHz).

This brief presents a modeling approach for a nonlinear series resistor–inductor–diode (RLD) circuit powered by either a direct or alternating voltage source—a configuration commonly encountered in power electronics and energy conversion systems. Due to the diode's nonlinear current–voltage characteristic and the inductor's dynamic response, the circuit is governed by a nonlinear differential equation. Because this equation lacks a closed-form analytical solution, a novel approximate solution is proposed by applying a g-function. This method enables accurate and robust computation across various operating conditions without relying on piecewise approximations or purely numerical solvers. The results are verified through MATLAB/SIMSCAPE simulations, demonstrating excellent agreement. Additionally, the MATLAB code is provided to support reproducibility and further research.

Stochastic computing (SC) is an emerging computing paradigm that offers excellent hardware efficiency and error tolerance. However, adopting SC in practical applications is not straightforward but faces serious challenges. In particular, a considerable overhead is imposed by the conversion between binary number and stochastic counterpart, which is usually performed by a stochastic number generator (SNG) and a binary counter. In this paper, we address this overhead issue by introducing a novel quantized SC architecture that shrinks the SNG hardware complexity significantly and a new approximate binary counter. To do this, we quantize binary numbers for SNGs to lower precision counterparts through several bit truncation schemes, which leads to an SNG overhead reduction. Also, we exploit a small-sized linear feedback shift register (LFSR) in the binary counter design to reduce its hardware resource consumption. When implemented in a 65-nm CMOS technology, the proposed quantized SNG and approximate binary counter reduce area and power by up to 68.3% and 80.6%, respectively, compared to the conventional full-precision SNG with an accurate counter. In addition, the proposed SC architecture with the LFSR-based counter does not deteriorate the stochastic computation accuracy beyond a certain degree of quantization. Besides, we demonstrate that the proposed SC schemes negligibly impact on processing quality with remarkably improved hardware efficiency by adopting it in a digital image processing application.

The negative group delay (NGD) circuit is uniquely capable of propagating arbitrary waveform signals with time advancement. Achieving significant NGD performance in practical applications, however, requires a multistage design approach. This article develops a design methodology for multistage low-pass (LP) NGD circuits based on RL-networks. After recalling the theoretical design equations enabling the determination of the multistage LP-NGD parameters based on the desired time advance and signal bandwidth, a design flow methodology is introduced. As proof-of-concept, a feasibility study of a multistage LP-NGD circuit, designed for a time advance of −100 ms, is conducted using a three-stage printed circuit board (PCB) consisting of RL-cells. Simulations in both the frequency and time domains confirm that the fabricated PCB prototype can propagate different waveform signals as expected, demonstrating the LP-NGD properties. Time-advance measurements with the PCB prototype further validate these LP-NGD effect findings. The proposed multistage design methodology provides a promising solution for addressing signal delay issues and offers new opportunities for innovative signal processing applications in future electronic systems.