Hongli Zhou, Liang Yao, Yongkang Feng, Zhengfeng Huang, Yingchun Lu
With the rise of the Internet and electronic devices, the security of network information is gaining attention, and the true random number generator (TRNG) is playing an increasingly crucial role in information security. TRNG, based on Boolean chaotic entropy source, has drawn significant interest due to its uncomplicated circuit design and minimal hardware resource usage. However, most existing structures consist of two‐input or three‐input logic devices, forming a complex multinode, geometrically symmetric Boolean chaotic network using multiple logic devices. This network configuration results in increased complexity and reduced throughput. This study introduces an entropy source based on Boolean chaos utilizing single‐node and four‐input XOR gates, which can be easily placed and routed on Xilinx Artix‐7 FPGA. It requires only 29 LUTs and 5 DFFs without any postprocessing, achieving a throughput of up to 700 Mb/s. The output of TRNG has successfully passed various tests including the autocorrelation test, NIST SP800‐22, NIST SP800‐90B, AIS‐31, and TESTU01 tests with favorable results. Furthermore, by applying a three‐stage XOR chain postprocessing on Xilinx Spartan‐6 FPGA and Xilinx Virtex‐6 FPGA, it has passed the NIST SP800‐22 and NIST SP800‐90B tests at 300 Mb/s. The structure was also tested using Xilinx Virtex‐6 FPGA under different temperature and voltage conditions, passing the NIST SP800‐90B IID test.
{"title":"Lightweight High‐Throughput TRNG Based on Single‐Node Boolean Chaotic Structure","authors":"Hongli Zhou, Liang Yao, Yongkang Feng, Zhengfeng Huang, Yingchun Lu","doi":"10.1002/cta.4265","DOIUrl":"https://doi.org/10.1002/cta.4265","url":null,"abstract":"With the rise of the Internet and electronic devices, the security of network information is gaining attention, and the true random number generator (TRNG) is playing an increasingly crucial role in information security. TRNG, based on Boolean chaotic entropy source, has drawn significant interest due to its uncomplicated circuit design and minimal hardware resource usage. However, most existing structures consist of two‐input or three‐input logic devices, forming a complex multinode, geometrically symmetric Boolean chaotic network using multiple logic devices. This network configuration results in increased complexity and reduced throughput. This study introduces an entropy source based on Boolean chaos utilizing single‐node and four‐input XOR gates, which can be easily placed and routed on Xilinx Artix‐7 FPGA. It requires only 29 LUTs and 5 DFFs without any postprocessing, achieving a throughput of up to 700 Mb/s. The output of TRNG has successfully passed various tests including the autocorrelation test, NIST SP800‐22, NIST SP800‐90B, AIS‐31, and TESTU01 tests with favorable results. Furthermore, by applying a three‐stage XOR chain postprocessing on Xilinx Spartan‐6 FPGA and Xilinx Virtex‐6 FPGA, it has passed the NIST SP800‐22 and NIST SP800‐90B tests at 300 Mb/s. The structure was also tested using Xilinx Virtex‐6 FPGA under different temperature and voltage conditions, passing the NIST SP800‐90B IID test.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142254683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Abbas Hoseinabadi, Mohammad Bagher Tavakoli, Mohammad Jalal Rastegar Fatemi, Farbod Setoudeh
The stepped‐impedance combline band pass filter (BPF) with novel input and output networks based on a new proposed J‐inverter, which increases the center frequency tuning range with constant bandwidth (BW), is discussed. The even and odd mode analysis shows that the stepped resonators provide the necessary conditions for the appropriate coupling coefficient to keep the BW constant. In order to create an appropriate quality factor, the new proposed J‐inverter is used. In the frequency response of the stopband region, three transition zeros (TZs) are generated, which two of TZs are controllable. The proposed tunable BPF has been fabricated on RO4003 substrate with a dielectric constant of 3.38 and 0.813 mm thickness. The size of the filter is compact and is only , where is the guided wavelength at the lower center frequency. The center frequency is equal to 1.723 GHz and a frequency tuning range from 1.2 GHz to 2.246 GHz with 100 MHz constant 3 dB absolute BW, the insertion loss of 1.4–3.17 dB and return loss of 17.8–25.9 dB is achieved.
{"title":"Varactor‐tuned bandpass filter using a microstrip stepped‐impedance combline filter and a new J‐inverter","authors":"Abbas Hoseinabadi, Mohammad Bagher Tavakoli, Mohammad Jalal Rastegar Fatemi, Farbod Setoudeh","doi":"10.1002/cta.4259","DOIUrl":"https://doi.org/10.1002/cta.4259","url":null,"abstract":"The stepped‐impedance combline band pass filter (BPF) with novel input and output networks based on a new proposed J‐inverter, which increases the center frequency tuning range with constant bandwidth (BW), is discussed. The even and odd mode analysis shows that the stepped resonators provide the necessary conditions for the appropriate coupling coefficient to keep the BW constant. In order to create an appropriate quality factor, the new proposed J‐inverter is used. In the frequency response of the stopband region, three transition zeros (TZs) are generated, which two of TZs are controllable. The proposed tunable BPF has been fabricated on RO4003 substrate with a dielectric constant of 3.38 and 0.813 mm thickness. The size of the filter is compact and is only , where is the guided wavelength at the lower center frequency. The center frequency is equal to 1.723 GHz and a frequency tuning range from 1.2 GHz to 2.246 GHz with 100 MHz constant 3 dB absolute BW, the insertion loss of 1.4–3.17 dB and return loss of 17.8–25.9 dB is achieved.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-09-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142254684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Wen Chen, Wenfen Liu, Ying Guo, Bin Yu, Yusheng Liu
Shadow is a lightweight AND‐RX block cipher adapted for resource‐constrained devices. In this paper, software and hardware optimizations are proposed respectively for Shadow to enhance its implementation performance. For software optimization, this paper first proposes a data pre‐processing scheme based on the structural characteristics of the round function. It further improves the optimization effect of the barrel shifter instruction while simplifying the implementation process of the round function. Note that the optimization strategy is also applicable to other AND‐RX ciphers. Secondly, this paper proposes a new NX operation implementation scheme that can effectively reduce its instruction cycles. In round‐based architecture, experimental results show that our scheme effectively reduces code size by 24.7%, Flash consumption by 12.6%, and total instruction cycles by 25.1%. Meanwhile, in the fully unrolled architecture, our scheme reduces code size by 30.8%, Flash consumption by 29.8%, and total instruction cycles by 28.1%. For hardware optimization, this paper proposes a low‐resource implementation scheme by constructing a generic formula for NX operation. In ASIC implementation, our scheme reduces hardware resources by 72.3%. In FPGA implementation, the number of LUTs and Slices is reduced by 30% and 28.6%, respectively. Overall, the proposed optimization scheme for Shadow has better performance in hardware and software implementation.
{"title":"A Compact Implementation of Shadow on an IoT Processor","authors":"Wen Chen, Wenfen Liu, Ying Guo, Bin Yu, Yusheng Liu","doi":"10.1002/cta.4272","DOIUrl":"https://doi.org/10.1002/cta.4272","url":null,"abstract":"Shadow is a lightweight AND‐RX block cipher adapted for resource‐constrained devices. In this paper, software and hardware optimizations are proposed respectively for Shadow to enhance its implementation performance. For software optimization, this paper first proposes a data pre‐processing scheme based on the structural characteristics of the round function. It further improves the optimization effect of the barrel shifter instruction while simplifying the implementation process of the round function. Note that the optimization strategy is also applicable to other AND‐RX ciphers. Secondly, this paper proposes a new NX operation implementation scheme that can effectively reduce its instruction cycles. In round‐based architecture, experimental results show that our scheme effectively reduces code size by 24.7%, Flash consumption by 12.6%, and total instruction cycles by 25.1%. Meanwhile, in the fully unrolled architecture, our scheme reduces code size by 30.8%, Flash consumption by 29.8%, and total instruction cycles by 28.1%. For hardware optimization, this paper proposes a low‐resource implementation scheme by constructing a generic formula for NX operation. In ASIC implementation, our scheme reduces hardware resources by 72.3%. In FPGA implementation, the number of LUTs and Slices is reduced by 30% and 28.6%, respectively. Overall, the proposed optimization scheme for Shadow has better performance in hardware and software implementation.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-09-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142254685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This study presents a novel approach to improve the efficiency and performance of a new proposed buck–boost converter. The buck–boost converter allows for voltage step‐up or step‐down operations, making it suitable for wide range applications. The proposed converter design incorporates innovative circuitry to enhance the overall system efficiency. Based on the findings, a new buck–boost converter topology is introduced, which offers improved voltage regulation, reduced losses, and increased power conversion efficiency compared to traditional converter designs. Simulation studies and experimental validations are conducted to assess the performance of the proposed new buck–boost converter. The results demonstrate significant improvements in power output and system stability of proposed converter compared to conventional converter configurations.
{"title":"Design, analysis, and experimental validation of proposed dual gain pseudo squared buck–boost converter","authors":"Shubham Kumar Singh, Anshul Agarwal","doi":"10.1002/cta.4232","DOIUrl":"https://doi.org/10.1002/cta.4232","url":null,"abstract":"This study presents a novel approach to improve the efficiency and performance of a new proposed buck–boost converter. The buck–boost converter allows for voltage step‐up or step‐down operations, making it suitable for wide range applications. The proposed converter design incorporates innovative circuitry to enhance the overall system efficiency. Based on the findings, a new buck–boost converter topology is introduced, which offers improved voltage regulation, reduced losses, and increased power conversion efficiency compared to traditional converter designs. Simulation studies and experimental validations are conducted to assess the performance of the proposed new buck–boost converter. The results demonstrate significant improvements in power output and system stability of proposed converter compared to conventional converter configurations.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142181724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Addressing issues of low input voltage in new energy generation systems such as fuel cells, a high step‐up three‐port DC–DC converter for fuel cell/battery hybrid power supply system is proposed. The proposed converter is evolved from Boost three‐port converter, and switch capacitor structure and diode capacitor voltage doubling unit are employed to achieve high voltage gain and low voltage stress. The three ports are connected to fuel cell, battery and load respectively, among which the flow of energy is realized. The steady state performance of this converter in various operating states and design of parameter are presented. Primary competitive advantages compared to similar converters include high voltage gain, continuous input current and its feature of common ground. Moreover, control strategy and compensators under three operating modes are designed to achieve stable output voltage and battery protection. Finally, a 100 W experimental prototype with 15 V input voltage and 24 V battery voltage is established to verify the stable and dynamic performance of the proposed converter.
针对燃料电池等新能源发电系统输入电压低的问题，提出了一种用于燃料电池/电池混合供电系统的高升压三端口 DC-DC 转换器。该转换器由 Boost 三端口转换器演变而来，采用开关电容器结构和二极管电容器电压倍增单元，以实现高电压增益和低电压应力。三个端口分别与燃料电池、电池和负载相连，实现了能量的流动。本文介绍了该转换器在各种工作状态下的稳态性能以及参数设计。与同类转换器相比，该转换器的主要竞争优势包括高电压增益、连续输入电流及其共地特性。此外，还设计了三种工作模式下的控制策略和补偿器，以实现稳定的输出电压和电池保护。最后，建立了一个输入电压为 15 V、电池电压为 24 V 的 100 W 实验原型，以验证所提转换器的稳定和动态性能。
{"title":"Switch Capacitor–Based High Step‐Up Three‐Port DC–DC Converter for Fuel Cell/Battery Integration","authors":"Liyin Bai, Zhidong Qi, Xuanhao Zhou, Kaihui Chu","doi":"10.1002/cta.4276","DOIUrl":"https://doi.org/10.1002/cta.4276","url":null,"abstract":"Addressing issues of low input voltage in new energy generation systems such as fuel cells, a high step‐up three‐port DC–DC converter for fuel cell/battery hybrid power supply system is proposed. The proposed converter is evolved from Boost three‐port converter, and switch capacitor structure and diode capacitor voltage doubling unit are employed to achieve high voltage gain and low voltage stress. The three ports are connected to fuel cell, battery and load respectively, among which the flow of energy is realized. The steady state performance of this converter in various operating states and design of parameter are presented. Primary competitive advantages compared to similar converters include high voltage gain, continuous input current and its feature of common ground. Moreover, control strategy and compensators under three operating modes are designed to achieve stable output voltage and battery protection. Finally, a 100 W experimental prototype with 15 V input voltage and 24 V battery voltage is established to verify the stable and dynamic performance of the proposed converter.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142181725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hybridized vehicular power supply (HVPS) are acquiring widespread adoption in various applications such as providing power for passenger or heavy‐duty electric vehicles, more‐electric ships, electrified rolling stocks, and more. Stability analysis is a critical issue for HVPS, but it presents significant challenges due to their prominent high‐dimensional and nonlinear characteristics. This paper presents a large‐signal stability analysis scheme for HVPS of rolling stocks, enabling the assessment of system stability under sudden load changes. Based on the state‐space averaging method, a mathematical model for the large‐signal behavior of the system is established. Subsequently, the small‐signal stability parameter range of the system is determined by analyzing the eigenvalues of the Jacobian matrix. To further analyze the stability of the system during large‐signal disturbances, a nonlinear decoupling transformation approach is employed to decompose the original high‐order state equations into multiple lower‐order equations. For the decoupled lower‐order subsystems, their stability is analyzed using phase portrait, and the region of attraction (ROA) is determined using the inverse trajectory method. Based on the stability analysis results, the controller is enhanced to bring the points outside the ROA back within it, thereby mitigating the transient instability phenomenon of the system. The effectiveness of the proposed method was demonstrated using two case studies.
{"title":"Large‐signal stability analysis for hybridized vehicular power supply systems of rolling stocks","authors":"Haoying Pei, Lijun Diao, Zheming Jin, Jia Zhang","doi":"10.1002/cta.4244","DOIUrl":"https://doi.org/10.1002/cta.4244","url":null,"abstract":"Hybridized vehicular power supply (HVPS) are acquiring widespread adoption in various applications such as providing power for passenger or heavy‐duty electric vehicles, more‐electric ships, electrified rolling stocks, and more. Stability analysis is a critical issue for HVPS, but it presents significant challenges due to their prominent high‐dimensional and nonlinear characteristics. This paper presents a large‐signal stability analysis scheme for HVPS of rolling stocks, enabling the assessment of system stability under sudden load changes. Based on the state‐space averaging method, a mathematical model for the large‐signal behavior of the system is established. Subsequently, the small‐signal stability parameter range of the system is determined by analyzing the eigenvalues of the Jacobian matrix. To further analyze the stability of the system during large‐signal disturbances, a nonlinear decoupling transformation approach is employed to decompose the original high‐order state equations into multiple lower‐order equations. For the decoupled lower‐order subsystems, their stability is analyzed using phase portrait, and the region of attraction (ROA) is determined using the inverse trajectory method. Based on the stability analysis results, the controller is enhanced to bring the points outside the ROA back within it, thereby mitigating the transient instability phenomenon of the system. The effectiveness of the proposed method was demonstrated using two case studies.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142181726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yingbao Liang, Fan Xie, Yanlin Liu, Bo Zhang, Dongyuan Qiu
A three‐level bidirectional buck/boost converter (TLBBBC) is suitable for power electronic systems with a high‐voltage DC link for its switches with half voltage. In order to achieve higher efficiency, a novel zero‐voltage switching (ZVS) TLBBBC is proposed in this paper to enable operation with higher switching frequencies. In the proposed ZVS TLBBBC, two identical ZVS cells, each composed of a resonant inductor, two snubber capacitors, and two resonant capacitors, are integrated with the conventional three‐level (TL) topology to enable soft switching in all four switches in both buck and boost modes. Here, one advantage is that soft‐switching conditions are ensured under conventional control methods without using the auxiliary switch or complex control methods. In addition, the soft‐switching region is derived, clearly illustrating the relationship between the duty cycle ratio and the power inductor current that ensures the soft‐switching condition. Hence, the soft‐switching region is beneficial for assisting in ZVS cell design and guiding the converter in running in ZVS. Then, the operation and design considerations of the proposed topology are analyzed in detail. Finally, the experimental results of an 800‐W prototype for both the boost and buck modes are presented to confirm the theoretical analysis.
{"title":"A Zero‐Voltage Switching Three‐Level Nonisolated Bidirectional DC/DC Converter With a Lossless Passive Component Auxiliary Circuit and Design‐Oriented Analysis","authors":"Yingbao Liang, Fan Xie, Yanlin Liu, Bo Zhang, Dongyuan Qiu","doi":"10.1002/cta.4269","DOIUrl":"https://doi.org/10.1002/cta.4269","url":null,"abstract":"A three‐level bidirectional buck/boost converter (TLBBBC) is suitable for power electronic systems with a high‐voltage DC link for its switches with half voltage. In order to achieve higher efficiency, a novel zero‐voltage switching (ZVS) TLBBBC is proposed in this paper to enable operation with higher switching frequencies. In the proposed ZVS TLBBBC, two identical ZVS cells, each composed of a resonant inductor, two snubber capacitors, and two resonant capacitors, are integrated with the conventional three‐level (TL) topology to enable soft switching in all four switches in both buck and boost modes. Here, one advantage is that soft‐switching conditions are ensured under conventional control methods without using the auxiliary switch or complex control methods. In addition, the soft‐switching region is derived, clearly illustrating the relationship between the duty cycle ratio and the power inductor current that ensures the soft‐switching condition. Hence, the soft‐switching region is beneficial for assisting in ZVS cell design and guiding the converter in running in ZVS. Then, the operation and design considerations of the proposed topology are analyzed in detail. Finally, the experimental results of an 800‐W prototype for both the boost and buck modes are presented to confirm the theoretical analysis.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142181727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Syed Enamur Rahaman, Santanu Dwari, Mirnal Kanti Mandal
The general electromagnetic (EM) theory has not yet been applied to the analysis of Class F (CF) power amplifier (PA). In this paper, an alternative approach for CF PA is presented based on the EM theory. Theoretical analysis shows that the CF PA can be divided into two broad categories, forward voltage gain, and reflected voltage gain PA. The existing CF PA belongs to the reflected voltage gain PA. Even though both the CF PAs have the same voltage gain, the PA with forward voltage gain provides higher fundamental power Ps,1@F and drain efficiency PAE@F than that CF PA with reflected voltage gain and Class B PA. This important conclusion is obtained as a result of this analysis, which cannot be explained by available theory in the literature. The theoretical analysis is validated at 2.2 GHz by fabrication and measurements. According to the results, Ps,1@B = 31.8 dBm and PAE@B = 53.27% in Class B PA. In CF PA with reflected voltage gain, Ps,1@F = 30.20 dBm and PAE@F = 48.6%. Both cases have lower power and PAE as compared to new category of CF PA. This new CF PA with forward voltage gain has, Ps,1@F = 33.04 dBm and PAE@F = 63.7%.
一般电磁（EM）理论尚未应用于 F 类（CF）功率放大器（PA）的分析。本文提出了一种基于电磁理论的 CF 功率放大器替代方法。理论分析表明，CF PA 可分为两大类，即正向电压增益 PA 和反射电压增益 PA。现有的 CF PA 属于反射电压增益 PA。尽管两种 CF 功率放大器的电压增益相同，但具有正向电压增益的功率放大器比具有反射电压增益的 CF 功率放大器和 B 类功率放大器提供更高的基本功率 Ps,1@F 和漏极效率 PAE@F。这一重要结论是通过分析得出的，而文献中的现有理论无法解释这一结论。理论分析在 2.2 GHz 频率下通过制造和测量得到了验证。结果显示，在 B 类功率放大器中，Ps,1@B = 31.8 dBm，PAE@B = 53.27%。在具有反射电压增益的 CF 功率放大器中，Ps,1@F = 30.20 dBm，PAE@F = 48.6%。与新型 CF 功率放大器相比，这两种情况的功率和 PAE 都较低。这种新型 CF 功率放大器的正向电压增益为 Ps,1@F = 33.04 dBm，PAE@F = 63.7%。
{"title":"Implementation of Electromagnetic Theory: Improved Analysis and Design for Class F Power Amplifier","authors":"Syed Enamur Rahaman, Santanu Dwari, Mirnal Kanti Mandal","doi":"10.1002/cta.4268","DOIUrl":"https://doi.org/10.1002/cta.4268","url":null,"abstract":"The general electromagnetic (EM) theory has not yet been applied to the analysis of Class F (CF) power amplifier (PA). In this paper, an alternative approach for CF PA is presented based on the EM theory. Theoretical analysis shows that the CF PA can be divided into two broad categories, forward voltage gain, and reflected voltage gain PA. The existing CF PA belongs to the reflected voltage gain PA. Even though both the CF PAs have the same voltage gain, the PA with forward voltage gain provides higher fundamental power <jats:italic>P</jats:italic><jats:sub><jats:italic>s</jats:italic>,1<jats:italic>@F</jats:italic></jats:sub> and drain efficiency <jats:italic>PAE</jats:italic><jats:sub><jats:italic>@F</jats:italic></jats:sub> than that CF PA with reflected voltage gain and Class B PA. This important conclusion is obtained as a result of this analysis, which cannot be explained by available theory in the literature. The theoretical analysis is validated at 2.2 GHz by fabrication and measurements. According to the results, <jats:italic>P</jats:italic><jats:sub><jats:italic>s</jats:italic>,1<jats:italic>@B</jats:italic></jats:sub> = 31.8 dBm and <jats:italic>PAE</jats:italic><jats:sub><jats:italic>@B</jats:italic></jats:sub> = 53.27% in Class B PA. In CF PA with reflected voltage gain, <jats:italic>P</jats:italic><jats:sub><jats:italic>s</jats:italic>,1<jats:italic>@F</jats:italic></jats:sub> = 30.20 dBm and <jats:italic>PAE</jats:italic><jats:sub><jats:italic>@F</jats:italic></jats:sub> = 48.6%. Both cases have lower power and PAE as compared to new category of CF PA. This new CF PA with forward voltage gain has, <jats:italic>P</jats:italic><jats:sub><jats:italic>s</jats:italic>,1<jats:italic>@F</jats:italic></jats:sub> = 33.04 dBm and <jats:italic>PAE</jats:italic><jats:sub><jats:italic>@F</jats:italic></jats:sub> = 63.7%.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142181729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Power quality issues encompass a spectrum of disturbances that affect the stability and reliability of the power supply. This study explores voltage‐related anomalies, including sags, surges, flickers, unbalances, harmonics, interruptions, and swells, examining their origins, characteristics, and repercussions. These issues arise from a myriad of sources, such as load fluctuations, equipment malfunctions, and grid dynamics. The ramifications of these disturbances extend to equipment malfunctions, reduced operational efficiency, and financial losses. Dynamic voltage restorer (DVRs) are series custom power devices for mitigating these voltage‐related anomalies and use real‐time monitoring and control to quickly inject exact voltages into the grid during disruptions, restoring voltage levels to acceptable levels. This study demonstrates the capacity of DVRs to successfully alleviate power quality concerns, hence improving equipment dependability and system stability by analyzing case studies and simulation findings. The control system used to supply switching signals to the voltage source converter (VSC) of the DVR is based on adaptive Bateman polynomial (ABMP). Traditional DVR control techniques often rely on fixed or linear control strategies, which may not adequately handle varying load conditions and disturbances. ABMP offers an adaptive approach where the control parameters can adjust dynamically based on real‐time system conditions. This adaptive capability enhances the accuracy of voltage restoration, ensuring that the DVR responds optimally to varying loads and disturbances. During voltage sag and swell conditions at the grid side, the VSC injects the compensating voltage in series with the feeder with a constant switching frequency. A battery energy‐supported system (BESS) based DVR is considered for the proposed system. The supply is connected to the critical and sensitive loads. The proposed control scheme is validated through extensive simulation and experimental results.
{"title":"Design and Control of DVR Based on Adaptive Bateman Polynomial for Power Quality Improvement","authors":"Kanchan Bala Rai, Narendra Kumar, Alka Singh","doi":"10.1002/cta.4270","DOIUrl":"https://doi.org/10.1002/cta.4270","url":null,"abstract":"Power quality issues encompass a spectrum of disturbances that affect the stability and reliability of the power supply. This study explores voltage‐related anomalies, including sags, surges, flickers, unbalances, harmonics, interruptions, and swells, examining their origins, characteristics, and repercussions. These issues arise from a myriad of sources, such as load fluctuations, equipment malfunctions, and grid dynamics. The ramifications of these disturbances extend to equipment malfunctions, reduced operational efficiency, and financial losses. Dynamic voltage restorer (DVRs) are series custom power devices for mitigating these voltage‐related anomalies and use real‐time monitoring and control to quickly inject exact voltages into the grid during disruptions, restoring voltage levels to acceptable levels. This study demonstrates the capacity of DVRs to successfully alleviate power quality concerns, hence improving equipment dependability and system stability by analyzing case studies and simulation findings. The control system used to supply switching signals to the voltage source converter (VSC) of the DVR is based on adaptive Bateman polynomial (ABMP). Traditional DVR control techniques often rely on fixed or linear control strategies, which may not adequately handle varying load conditions and disturbances. ABMP offers an adaptive approach where the control parameters can adjust dynamically based on real‐time system conditions. This adaptive capability enhances the accuracy of voltage restoration, ensuring that the DVR responds optimally to varying loads and disturbances. During voltage sag and swell conditions at the grid side, the VSC injects the compensating voltage in series with the feeder with a constant switching frequency. A battery energy‐supported system (BESS) based DVR is considered for the proposed system. The supply is connected to the critical and sensitive loads. The proposed control scheme is validated through extensive simulation and experimental results.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142181728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Indira Damarla, Bindu Vadlamudi, Venmathi Mahendran, K. Dhananjay Rao
In this paper, the performance of the 3Φ, 6/4 switched reluctance (SR) motor drive has been analyzed using the different power converter topologies. The main objective is to identify the most suitable converter topology for SR motor drive fed electric vehicle (EV) applications. The various power converters such as dissipative, capacitive, magnetic, and bridge converters have been reviewed in terms of operating principle and the calculation of torque ripple. To analyze the drive performance, a comparative analysis is conducted between various power converter configurations including R‐dump, C‐dump, C‐dump with freewheeling transistor (FWT), and asymmetric bridge (ASB) converter. The torque ripple is evaluated for different converters, and it has been claimed that ASB converter has less torque ripple than other topologies. MATLAB/Simulink software tool is used to validate the drive performance for various configurations. A hardware setup includes a FPGA processor of Xilinx Spartan has been embedded to verify the experimental results with the Simulink results.
{"title":"Analysis of Torque Ripple Investigation on Three‐Phase SR Motor Drive for EV Applications","authors":"Indira Damarla, Bindu Vadlamudi, Venmathi Mahendran, K. Dhananjay Rao","doi":"10.1002/cta.4266","DOIUrl":"https://doi.org/10.1002/cta.4266","url":null,"abstract":"In this paper, the performance of the 3Φ, 6/4 switched reluctance (SR) motor drive has been analyzed using the different power converter topologies. The main objective is to identify the most suitable converter topology for SR motor drive fed electric vehicle (EV) applications. The various power converters such as dissipative, capacitive, magnetic, and bridge converters have been reviewed in terms of operating principle and the calculation of torque ripple. To analyze the drive performance, a comparative analysis is conducted between various power converter configurations including R‐dump, C‐dump, C‐dump with freewheeling transistor (FWT), and asymmetric bridge (ASB) converter. The torque ripple is evaluated for different converters, and it has been claimed that ASB converter has less torque ripple than other topologies. MATLAB/Simulink software tool is used to validate the drive performance for various configurations. A hardware setup includes a FPGA processor of Xilinx Spartan has been embedded to verify the experimental results with the Simulink results.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142181730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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