Low power content addressable memory using common match line scheme for high performance processors

Abstract

Content Addressable Memory (CAM) is utilized in Artificial Neural Networks, data compression, IP packet filtering, and network routers due to its high performance in the microprocessor. However, the use of CAM is limited because of its increased power consumption, especially in high capacitive Match-Lines (ML). The activation of every comparison circuit on every clock cycle is primarily responsible for the significant power dissipation, which leads to increased recharge activity and multiple transition occurrences in the ML. In order to overcome this issue, a novel Common Match Line Scheme (CMS) with a Pull Up/Pull Down (PUPD) Circuit is proposed. The new design of the CMS CAM architecture leverages by utilizing these technique, the mismatched tagline entries are kept in the pre-discharged phases, and only the matching tagline entry gets charged. Consequently, these approaches effectively reduce pre-charge activity and mitigate evaluate-power, thereby alleviating power dissipation concerns associated with CAM 13–45% and reducing delay 3–16% while comparing to the existing architectures without significant impact on the performance of the processor. Proposed CMS CAM outperforms the existing architectures in terms of noise also with minimal area overhead and it is a technology independent one which can be used in high performance microprocessor systems.