TSV Built-In Self-Repair Architecture for Lifespan Reliability Enhancement of HBM

Abstract

High-bandwidth memory (HBM) is one of the 3-D stacked memory standards that demonstrate high performance, including high bandwidth, large capacity, and low power consumption. However, despite these advantages, issues related to reliability and yield have imposed limitations on mass production. Various methodologies to enhance the reliability of HBM have been proposed, such as built-in self-repair (BISR) architectures and error correction code algorithms. Nevertheless, ensuring the reliability of through-silicon vias (TSV) remains a challenging problem. Existing built-in architectures aiming to enhance TSV reliability often incur significant hardware overhead, limiting practical applications. In this article, an innovative TSV BISR architecture that can detect and repair permanent TSV faults in real time at the user stage is proposed. The proposed architecture significantly enhances the reliability of HBM while implementing it with minimal hardware overhead. Furthermore, it effectively identifies both temporary errors and permanent TSV faults, enabling efficient TSV repairs. Through fast and accurate TSV fault repair, the proposed architecture substantially improves the reliability of HBM.