Optimal Design of Low-Power Ultra-Wideband Low-Noise Transconductance Amplifier in 0.18 µm CMOS

Abstract

A low-noise amplifier (LNA) is one of the most crucial components of a communication system. The current low-noise amplifier design faces challenges due to intrinsic noise sources in CMOS transistors and trade-offs to maximize gain and bandwidth. Hence the Optimal design of a low-power ultra-wideband low-noise transconductance amplifier in 0.18 µm CMOS is introduced to minimize the noise figure of the amplifier. Ultra wideband (UWB) signals cover a wide frequency range making it challenging to achieve good input and output matching across the entire band. Thus, Cascode inductive degenerative using pi matching network enhances input–output matching by providing impedance transformation, matching source impedance to low input impedance, and improving power transfer rate. However, the cascode configuration with pi matching offers superior performance over a wide frequency range, but it requires careful consideration of gain and noise figures. Therefore, a current reuse technique is utilized to improve gain and reduce noise figures by optimizing the distribution of bias currents and enhancing the overall performance of the amplifier. Furthermore, the main design challenge for LNAs is achieving high linearity in interference-filled environments. Hence novel Cascade inductive degenerative using T matching network addresses low-frequency signal interference by utilizing multiple amplifier stages for gain and high linearity. Thus, the result obtained showed that the proposed model outperforms the existing design with high gain of 17.7 dB, high input return loss of 10.6 dB, high FOM of 24.4 and low noise figures of 0.573 dB, thus improves the overall performance of the system.