{"title":"An 8 Gb/s Far-End Crosstalk Cancelation and FFE Co-Designed TX Output Driver","authors":"Guan-Yu Chen;Tai-Cheng Lee","doi":"10.1109/LSSC.2024.3439399","DOIUrl":null,"url":null,"abstract":"This letter describes a single-ended transmitter (TX) output driver, which combines a feed-forward equalizer (FFE) and a far-end crosstalk (FEXT) canceller. The proposed output driver reduces the crosstalk-induced jitter (CIJ) between the two parallel coupled microstrip lines while preserving the inherent high-frequency boosting signal for the channel loss compensation. A prototype operating at a supply voltage of 0.9 V was fabricated in a 28-nm CMOS technology, occupying an area of \n<inline-formula> <tex-math>$0.025~{\\text {mm}^{2}}$ </tex-math></inline-formula>\n. This prototype reduces the peak-to-peak jitter and CIJ by 48% (29 ps) and 114%, respectively, at 8 Gb/s. Furthermore, it increases the horizontal eye-opening (BER < 1E-12) by 34%, with an energy efficiency of 1.08 pJ/bit/channel.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"227-230"},"PeriodicalIF":2.2000,"publicationDate":"2024-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Solid-State Circuits Letters","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/10623838/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
Abstract
This letter describes a single-ended transmitter (TX) output driver, which combines a feed-forward equalizer (FFE) and a far-end crosstalk (FEXT) canceller. The proposed output driver reduces the crosstalk-induced jitter (CIJ) between the two parallel coupled microstrip lines while preserving the inherent high-frequency boosting signal for the channel loss compensation. A prototype operating at a supply voltage of 0.9 V was fabricated in a 28-nm CMOS technology, occupying an area of
$0.025~{\text {mm}^{2}}$
. This prototype reduces the peak-to-peak jitter and CIJ by 48% (29 ps) and 114%, respectively, at 8 Gb/s. Furthermore, it increases the horizontal eye-opening (BER < 1E-12) by 34%, with an energy efficiency of 1.08 pJ/bit/channel.