A class AB ultra-low-power asymmetrical structured current multiplier

Abstract

An ultra-low power (ULP) class-AB four-quadrant current multiplier is introduced with a new power and area-saving technique based on asymmetrical structures such as direct current copying (DCC) and an asymmetrical transconductor (A-g_m). The DCC technique decreases the bias current and chip area by copying them directly from the lower current branches. Additionally; it enables direct voltage biasing and current branch elimination, resulting in lower decreased standby and dynamic power and smaller chip area. The newly released A-g_m, featuring asymmetrical input transistors, enables a further reduction in current bias with minimal distortion but a higher input modulation index (M.I.) than previous works. Furthermore, a Wilson active load with modified transistor dimensions was applied to implement the structure in a conventional n-well 180 nm TSMC process. Simulation results verified by Cadence Virtuoso software demonstrate superior achievements in power and area compared to previous works, despite using a more backward technology. For a $\pm$ 0.35 V voltage power supply, the multiplier has a 1.8 nW standby power and a total harmonic distortion (THD) of −30 dB for an input M.I. of 12.64.