An Efficient Low-Power BIST for Automotive SoC With Periodic Pattern Type Selection

Abstract

In the realm of automotive System-on-Chip (SoC), scan-based logic built-in self-test (LBIST) is commonly utilized for in-system testing, primarily for its cost-effectiveness. Nevertheless, this approach encounters challenges, particularly in attaining high-test coverage within constrained test times. The challenge intensifies when implementing low-power patterns, as it further complicates the achievement of adequate test coverage. To overcome these hurdles, this article introduces a novel testing methodology that enhances test coverage using low-toggled patterns. This method consists of two primary phases. Initially, it involves grouping and pairing scan cells (SCs), ensuring adjacent placement of paired cells. The following phase involves the generation of low-toggled patterns, tailored to the specific arrangement of SCs. To optimally detect as many previously undetected faults as possible, this method applies the low-power pattern selectively to particular scan groups. Furthermore, the scan group subjected to low-power patterns alternates after a certain number of patterns. Experimental results demonstrate the superiority of this proposed method in both fault detection and power reduction, in comparison to earlier methods.