Pub Date : 2026-02-20DOI: 10.1109/TCAD.2026.3661658
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Pub Date : 2026-01-21DOI: 10.1109/TCAD.2025.3650328
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Pub Date : 2026-01-06DOI: 10.1109/TCAD.2025.3641269
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Pub Date : 2025-11-25DOI: 10.1109/TCAD.2025.3637444
{"title":"2025 Index IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","authors":"","doi":"10.1109/TCAD.2025.3637444","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3637444","url":null,"abstract":"","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 12","pages":"4842-4927"},"PeriodicalIF":2.9,"publicationDate":"2025-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11268960","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145612167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-21DOI: 10.1109/TCAD.2025.3629792
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Pub Date : 2025-10-21DOI: 10.1109/TCAD.2025.3613885
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Pub Date : 2025-09-16DOI: 10.1109/TCAD.2025.3590127
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Pub Date : 2025-09-10DOI: 10.1109/TCAD.2025.3590129
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This article proposes an uncertainty quantification (UQ)-incorporated design optimization technique that integrates UQ, considering the statistical characteristics of sensing margin with machine learning (ML) for the design of bitline sense amplifiers (BLSAs) in dynamic random access memory (DRAM), including offset compensation operation. The increased offset due to process variation exacerbated by device scaling degrades the reliability of DRAM read operations, making quantitative analysis of process variation essential. Conventional Monte Carlo (MC)-based UQ analysis provides high accuracy but requires extensive simulation costs. Accordingly, this study systematically defines key input and output variables for conventional BLSA and two representative offset compensation BLSA structures, introduces Sobol sequence-based quasi-MC (QMC) sampling to improve simulation efficiency, and generalizes the Standard UQ methodology to predict statistical distributions of circuit performance parameters under process variation. Furthermore, a three-stage UQ algorithm that sequentially learns nominal, mean, and standard deviation values is proposed to enhance the efficiency of ML model training. HSPICE simulation results based on the TSMC 65-nm process demonstrated that the proposed three-stage UQ method reduced the simulation time required for ML training data generation by an average of 43% compared to the standard UQ method and achieved excellent prediction performance even in data-limited environments. Additionally, design optimization combined with Bayesian optimization (BO) confirmed performance improvements across all circuit structures. The methodology presented in this study enables effective process variation-aware optimization for DRAM designs requiring high reliability and yield and is expected to contribute to next-generation memory circuit design automation.
{"title":"Machine Learning-Based Uncertainty Quantification and Design Optimization for Offset Compensation Sense Amplifiers in DRAMs","authors":"Hyerin Lee;Dongyeong Kim;Geon Kim;Suyeon Kim;Jewon Park;Sinwook Kim;Hyeona Seo;Chaehyuk Lim;Sowon Kim;Juwon Lee;Jeonghyeon Yun;Seung-Hwan Kim;Yongbok Lee;Suhyung Park;Myeongjin Kim;Myoungjin Lee","doi":"10.1109/TCAD.2025.3603112","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3603112","url":null,"abstract":"This article proposes an uncertainty quantification (UQ)-incorporated design optimization technique that integrates UQ, considering the statistical characteristics of sensing margin with machine learning (ML) for the design of bitline sense amplifiers (BLSAs) in dynamic random access memory (DRAM), including offset compensation operation. The increased offset due to process variation exacerbated by device scaling degrades the reliability of DRAM read operations, making quantitative analysis of process variation essential. Conventional Monte Carlo (MC)-based UQ analysis provides high accuracy but requires extensive simulation costs. Accordingly, this study systematically defines key input and output variables for conventional BLSA and two representative offset compensation BLSA structures, introduces Sobol sequence-based quasi-MC (QMC) sampling to improve simulation efficiency, and generalizes the Standard UQ methodology to predict statistical distributions of circuit performance parameters under process variation. Furthermore, a three-stage UQ algorithm that sequentially learns nominal, mean, and standard deviation values is proposed to enhance the efficiency of ML model training. HSPICE simulation results based on the TSMC 65-nm process demonstrated that the proposed three-stage UQ method reduced the simulation time required for ML training data generation by an average of 43% compared to the standard UQ method and achieved excellent prediction performance even in data-limited environments. Additionally, design optimization combined with Bayesian optimization (BO) confirmed performance improvements across all circuit structures. The methodology presented in this study enables effective process variation-aware optimization for DRAM designs requiring high reliability and yield and is expected to contribute to next-generation memory circuit design automation.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 3","pages":"1473-1486"},"PeriodicalIF":2.9,"publicationDate":"2025-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146223849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Fixing bugs in hardware design code has become a challenging task due to the increasing complexity of modern circuit designs. As a result, automated program repair (APR) techniques have been proposed to synthesize patches for bugs in hardware designs and have achieved promising results. However, existing techniques are still limited in synthesizing expressions for complex bugs. In this work, we explore the possibility of addressing complex bugs by proposing SRepair, a novel symbolic regression-based repair technique. The key novelty of SRepair lies in three aspects: 1) we propose a novel expression modification encoding (EME) that enables fine-grained adjustments to buggy expressions; 2) we introduce expression synthesis-based templates that allow for flexible and expressive repairs; and 3) we develop a novel symbolic regression network (SNR)-based synthesis algorithm that effectively synthesizes complex expressions. Experimental results on the four peer-reviewed datasets demonstrate that SRepair correctly fixes 56 bugs out of 112 bugs, which achieves 43.6% and 194.7% improvement over the previous state-of-the-art RTL-Repair (39 bugs) and CirFix (19 bugs). To evaluate the generalizability of SRepair, we further construct an augmented dataset of 282 bugs by mutating hardware designs. SRepair shows its better generalizability by correctly fixing 127 bugs, reaching 217.5% improvement over the best approach.
{"title":"SRepair: Symbolic Regression-Based Repair for Hardware Design Code","authors":"Zizhen Liu;Deheng Yang;Xiaoguang Mao;Jiayu He;Guangda Zhang;Yan Lei;Jiang Wu","doi":"10.1109/TCAD.2025.3603097","DOIUrl":"https://doi.org/10.1109/TCAD.2025.3603097","url":null,"abstract":"Fixing bugs in hardware design code has become a challenging task due to the increasing complexity of modern circuit designs. As a result, automated program repair (APR) techniques have been proposed to synthesize patches for bugs in hardware designs and have achieved promising results. However, existing techniques are still limited in synthesizing expressions for complex bugs. In this work, we explore the possibility of addressing complex bugs by proposing <sc>SRepair</small>, a novel symbolic regression-based repair technique. The key novelty of <sc>SRepair</small> lies in three aspects: 1) we propose a novel expression modification encoding (EME) that enables fine-grained adjustments to buggy expressions; 2) we introduce expression synthesis-based templates that allow for flexible and expressive repairs; and 3) we develop a novel symbolic regression network (SNR)-based synthesis algorithm that effectively synthesizes complex expressions. Experimental results on the four peer-reviewed datasets demonstrate that <sc>SRepair</small> correctly fixes 56 bugs out of 112 bugs, which achieves 43.6% and 194.7% improvement over the previous state-of-the-art <sc>RTL-Repair</small> (39 bugs) and C<sc>irFix</small> (19 bugs). To evaluate the generalizability of <sc>SRepair</small>, we further construct an augmented dataset of 282 bugs by mutating hardware designs. <sc>SRepair</small> shows its better generalizability by correctly fixing 127 bugs, reaching 217.5% improvement over the best approach.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 3","pages":"1509-1522"},"PeriodicalIF":2.9,"publicationDate":"2025-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146223737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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