{"title":"Design and Utilization of Multiskewed Multibit Flip-Flop Cells for Timing Optimization: Design and Technology Co-Optimization Approach","authors":"Suwan Kim;Taewhan Kim","doi":"10.1109/TCAD.2024.3457834","DOIUrl":null,"url":null,"abstract":"Utilizing multibit flip-flops (MBFFs) in circuit implementation offers a considerable saving on the dynamic power dissipated at the clock networks. However, indiscreetly allocating MBFFs by grouping single-bit flip-flops at the logic synthesis or placement stage in order to greedily save dynamic power severely hinders a full applicability of useful clock skew scheduling to the individual flip-flops in MBFFs, failing in effectively optimizing circuit timing. This is because the two internal clock inverters, consequently, the clock skew value, in an MBFF are shared by all of the flip-flops in the MBFF. This work overcomes this inherent limitation of inflexibility in MBFFs for useful clock skew scheduling by proposing a comprehensive design and technology co-optimization (DTCO) framework. To this end, we devise a new layout of MBFF cells called multiskewed MBFF layout, in which different clock skew values can be set to the individual internal flip-flops at the cost of additional internal clock inverters. With the multiskewed MBFFs, we propose a three-step DTCO flow: 1) DTCO-based flip-flop clustering at the logic stage, which clusters flip-flops considering multiskewed MBFFs; 2) DTCO based on in-place MBFF debanking technique at the preroute stage to facilitate the full applicability of useful skew scheduling at the subsequent stages; and 3) DTCO utilizing MBFF cell layout diversification at the post-route stage, by which useful clock skew scheduling can effectively resolve timing violations. Through experiments with OpenCores benchmark circuits, it is shown that our proposed DTCO flow of reinforcing the effectiveness of useful clock skew scheduling on circuits with MBFF instances is able to reduce the worst and total negative slacks by 36.73% and 50.76%, respectively, while decreasing the clock and total power consumption by 43.46% and 22.70% over that produced by the conventional flow using a state-of-the-art commercial tool.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 3","pages":"1084-1097"},"PeriodicalIF":2.9000,"publicationDate":"2024-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","FirstCategoryId":"94","ListUrlMain":"https://ieeexplore.ieee.org/document/10677402/","RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
Abstract
Utilizing multibit flip-flops (MBFFs) in circuit implementation offers a considerable saving on the dynamic power dissipated at the clock networks. However, indiscreetly allocating MBFFs by grouping single-bit flip-flops at the logic synthesis or placement stage in order to greedily save dynamic power severely hinders a full applicability of useful clock skew scheduling to the individual flip-flops in MBFFs, failing in effectively optimizing circuit timing. This is because the two internal clock inverters, consequently, the clock skew value, in an MBFF are shared by all of the flip-flops in the MBFF. This work overcomes this inherent limitation of inflexibility in MBFFs for useful clock skew scheduling by proposing a comprehensive design and technology co-optimization (DTCO) framework. To this end, we devise a new layout of MBFF cells called multiskewed MBFF layout, in which different clock skew values can be set to the individual internal flip-flops at the cost of additional internal clock inverters. With the multiskewed MBFFs, we propose a three-step DTCO flow: 1) DTCO-based flip-flop clustering at the logic stage, which clusters flip-flops considering multiskewed MBFFs; 2) DTCO based on in-place MBFF debanking technique at the preroute stage to facilitate the full applicability of useful skew scheduling at the subsequent stages; and 3) DTCO utilizing MBFF cell layout diversification at the post-route stage, by which useful clock skew scheduling can effectively resolve timing violations. Through experiments with OpenCores benchmark circuits, it is shown that our proposed DTCO flow of reinforcing the effectiveness of useful clock skew scheduling on circuits with MBFF instances is able to reduce the worst and total negative slacks by 36.73% and 50.76%, respectively, while decreasing the clock and total power consumption by 43.46% and 22.70% over that produced by the conventional flow using a state-of-the-art commercial tool.
期刊介绍:
The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components. The aids include methods, models, algorithms, and man-machine interfaces for system-level, physical and logical design including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, hardware-software co-design and documentation of integrated circuit and system designs of all complexities. Design tools and techniques for evaluating and designing integrated circuits and systems for metrics such as performance, power, reliability, testability, and security are a focus.