Design and Utilization of Multiskewed Multibit Flip-Flop Cells for Timing Optimization: Design and Technology Co-Optimization Approach

IF 2.9 3区 计算机科学 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2024-09-11 DOI:10.1109/TCAD.2024.3457834
Suwan Kim;Taewhan Kim
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Abstract

Utilizing multibit flip-flops (MBFFs) in circuit implementation offers a considerable saving on the dynamic power dissipated at the clock networks. However, indiscreetly allocating MBFFs by grouping single-bit flip-flops at the logic synthesis or placement stage in order to greedily save dynamic power severely hinders a full applicability of useful clock skew scheduling to the individual flip-flops in MBFFs, failing in effectively optimizing circuit timing. This is because the two internal clock inverters, consequently, the clock skew value, in an MBFF are shared by all of the flip-flops in the MBFF. This work overcomes this inherent limitation of inflexibility in MBFFs for useful clock skew scheduling by proposing a comprehensive design and technology co-optimization (DTCO) framework. To this end, we devise a new layout of MBFF cells called multiskewed MBFF layout, in which different clock skew values can be set to the individual internal flip-flops at the cost of additional internal clock inverters. With the multiskewed MBFFs, we propose a three-step DTCO flow: 1) DTCO-based flip-flop clustering at the logic stage, which clusters flip-flops considering multiskewed MBFFs; 2) DTCO based on in-place MBFF debanking technique at the preroute stage to facilitate the full applicability of useful skew scheduling at the subsequent stages; and 3) DTCO utilizing MBFF cell layout diversification at the post-route stage, by which useful clock skew scheduling can effectively resolve timing violations. Through experiments with OpenCores benchmark circuits, it is shown that our proposed DTCO flow of reinforcing the effectiveness of useful clock skew scheduling on circuits with MBFF instances is able to reduce the worst and total negative slacks by 36.73% and 50.76%, respectively, while decreasing the clock and total power consumption by 43.46% and 22.70% over that produced by the conventional flow using a state-of-the-art commercial tool.
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设计和利用多倾斜多比特触发器单元实现时序优化:设计与技术协同优化方法
在电路实现中使用多比特触发器(mbff)可以大大节省时钟网络的动态功耗。然而,为了节省动态功率,在逻辑合成或放置阶段通过将单个触发器分组来不谨慎地分配mbff,严重阻碍了有效的时钟倾斜调度对mbff中单个触发器的充分适用,无法有效地优化电路时序。这是因为两个内部时钟逆变器,因此,时钟倾斜值,在MBFF中由MBFF中的所有触发器共享。本工作通过提出一个全面的设计和技术协同优化(DTCO)框架,克服了mbff中缺乏灵活性的固有限制,实现了有用的时钟倾斜调度。为此,我们设计了一种新的MBFF单元布局,称为多倾斜MBFF布局,在这种布局中,可以为单个内部触发器设置不同的时钟倾斜值,而代价是增加内部时钟逆变器。针对多弯曲mbff,我们提出了一个三步DTCO流程:1)逻辑阶段基于DTCO的触发器聚类,对考虑多弯曲mbff的触发器进行聚类;(2)基于现场MBFF脱银行技术的预先DTCO,以促进有用的倾斜调度在后续阶段的充分应用;3)在路由后阶段利用MBFF小区布局多样化的DTCO,有效地解决了时钟偏差调度问题。通过对OpenCores基准电路的实验表明,我们提出的在MBFF实例电路上增强有用时钟倾斜调度有效性的DTCO流能够将最坏和总负时延分别减少36.73%和50.76%,同时将时钟和总功耗降低43.46%和22.70%,而传统流使用最先进的商业工具。
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来源期刊
CiteScore
5.60
自引率
13.80%
发文量
500
审稿时长
7 months
期刊介绍: The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components. The aids include methods, models, algorithms, and man-machine interfaces for system-level, physical and logical design including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, hardware-software co-design and documentation of integrated circuit and system designs of all complexities. Design tools and techniques for evaluating and designing integrated circuits and systems for metrics such as performance, power, reliability, testability, and security are a focus.
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