Signal Integrity Augmentation Techniques for the Design of 64-GBaud Coherent Transimpedance Amplifier in 90-nm SiGe BiCMOS

IF 5.2 1区 工程技术 Q1 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-09-04 DOI:10.1109/TCSI.2024.3450700
Shuaizhe Ma;Nianquan Ran;Xi Liu;Yifei Xia;Songqin Xu;Wei Huang;Chen Tan;Jing Li;Zhenyu Yin;Shaoheng Lin;Jianhua Pan;Zhe Chen;Chaoxuan Zhang;Wu Wen;Quan Pan;Zhongming Xue;Xiaoyan Gui;Li Geng;Dan Li
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Abstract

This paper presents signal integrity augmentation design techniques in a 64-GBaud transimpedance amplifier (TIA) for coherent optical communication. In the FE-TIA, a bonding wire ringing reduction technique and an input DC current cancellation (IDCC) loop adapted for coherent communication are proposed. In the post amplifiers, a group delay variation (GDV) friendly bandwidth boosting technique is proposed to achieve optimal time domain performance. A non-linearity cancellation technique and a high-linearity gain control approach are proposed in both circuit and system levels. These signal integrity augmentation techniques form a toolkit to solve the design challenges in bandwidth, linearity, GDV, ringing, offset, crosstalk, etc. in high-speed high-order modulation communication. Fabricated in a 90-nm SiGe BiCMOS technology, the TIA shows input-referred noise current density of 15.1 pA/ $\surd $ Hz, bandwidth of over 40 GHz with GDV less than ±3.75 ps. The TIA gain can be adjusted between $150~\Omega $ - 5 K $\Omega $ , which enables maximum overload input current of 3 mApp. The total harmonic distortion (THD) is less than 3% and the crosstalk between two channels is less than -3 dB. The chip consumes 264 mW from 3.3 V supply.
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采用 90 纳米 SiGe BiCMOS 设计 64-GBaud 相干互阻抗放大器的信号完整性增强技术
本文介绍了用于相干光通信的 64-GBaud 互阻抗放大器(TIA)中的信号完整性增强设计技术。在前置放大器(FE-TIA)中,提出了一种减少键合线振铃的技术和一种适用于相干通信的输入直流电流消除(IDCC)环路。在后置放大器中,提出了一种群延迟变化(GDV)友好型带宽提升技术,以实现最佳时域性能。在电路和系统层面提出了非线性消除技术和高线性增益控制方法。这些信号完整性增强技术形成了一个工具包,用于解决高速高阶调制通信中的带宽、线性度、GDV、振铃、偏移、串扰等设计难题。TIA 采用 90 nm SiGe BiCMOS 技术制造,输入参考噪声电流密度为 15.1 pA/ $\surd $ Hz,带宽超过 40 GHz,GDV 小于 ±3.75 ps。TIA 增益可在 150~\Omega $ - 5 K $\Omega $ 之间调节,从而使最大过载输入电流达到 3 mApp。总谐波失真(THD)小于 3%,两个通道之间的串音小于 -3 dB。芯片的 3.3 V 电源功耗为 264 mW。
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来源期刊
IEEE Transactions on Circuits and Systems I: Regular Papers
IEEE Transactions on Circuits and Systems I: Regular Papers 工程技术-工程:电子与电气
CiteScore
9.80
自引率
11.80%
发文量
441
审稿时长
2 months
期刊介绍: TCAS I publishes regular papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes: - Circuits: Analog, Digital and Mixed Signal Circuits and Systems - Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic - Circuits and Systems, Power Electronics and Systems - Software for Analog-and-Logic Circuits and Systems - Control aspects of Circuits and Systems.
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