A Single-Ended PAM-4 Transmitter Using Unstacked Tailless CML Driver and Coefficient-Corrected FFE for Memory Interfaces

Abstract

This paper presents a single-ended four-level pulse-amplitude modulation (PAM-4) transmitter using an unstacked tailless current-mode logic (CML) driver for memory interfaces. Compared with the voltage-mode (VM) driver commonly used for single-ended memory interfaces, the proposed CML driver has stable termination for impedance matching and a small pre-driver with low dynamic power consumption, which allow the transmitter to achieve a higher data rate and a better total energy efficiency. The unstacked driver structure with an auxiliary leg and a current calibration scheme leads to high PAM-4 linearity by compensating for channel-length modulation that causes current source variation while occupying a small area. The strength of the feed-forward equalization (FFE) distorted by channel-length modulation is also compensated by an additional pulse of the proposed coefficient-corrected equalization. A prototype chip fabricated in a 65-nm CMOS process has an area of 0.0172 mm $^{2}{}$ . It achieves a data rate of 34 Gb/s/pin with an energy efficiency of 0.60 pJ/bit and a level separation mismatch ratio (RLM) of 0.987.