A 4×6.25-Gb/s Serial Link Transmitter Core in 0.18-μm CMOS for High-Speed Front-End ASICs

Abstract

High-speed serial link transmitters have been widely integrated in front-end application specified integrated circuits (ASICs). However, it is difficult to achieve high data bandwidth, low power consumption, and low jitter at the same time. In this article, a $4\times 6.25$ -Gb/s serial link transmitter core has been designed for high-speed front-end ASICs. The transmitter core is implemented in a commercial 0.18- $\mu $ m CMOS technology. The core consists of a common ring-oscillator-based phase-locked loop (PLL) and four individual transmitter channels. Each channel contains a two-stage 20:2 serializer, a two-tap half-rate feed-forward equalizer (FFE), and a clock manager circuit. With a new architecture of the final-stage serializer and half-rate FFE and an optimized selection scheme of the flip-flops in the serializer, the number of current mode logic (CML) devices is decreased and the total power consumption is significantly reduced compared with previous works, while maintaining high data bandwidth and low jitter. To validate the designed transmitter core, a prototype chip has been fabricated and tested. The test results show that the transmitter core operates from 3.5 to 6.75 Gb/s. At a data rate of 6.25 Gb/s, the PLL outputs a 3.125-GHz clock, with a phase jitter of 1.006-ps rms, and the total jitter (Tj) of the output data is 45.5 ps at a bit error rate (BER) of $1\times 10^{-{12}}$ . The core occupies an area of 0.44 mm2 and consumes 27.8 mW/Gb/s at a 1.8-V supply.