Pub Date : 2025-03-17DOI: 10.1109/TNS.2025.3549806
{"title":"IEEE Transactions on Nuclear Science information for authors","authors":"","doi":"10.1109/TNS.2025.3549806","DOIUrl":"https://doi.org/10.1109/TNS.2025.3549806","url":null,"abstract":"","PeriodicalId":13406,"journal":{"name":"IEEE Transactions on Nuclear Science","volume":"72 3","pages":"C3-C3"},"PeriodicalIF":1.9,"publicationDate":"2025-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10930343","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143645203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-17DOI: 10.1109/TNS.2025.3548741
{"title":"IEEE Transactions on Nuclear Science information for authors","authors":"","doi":"10.1109/TNS.2025.3548741","DOIUrl":"https://doi.org/10.1109/TNS.2025.3548741","url":null,"abstract":"","PeriodicalId":13406,"journal":{"name":"IEEE Transactions on Nuclear Science","volume":"72 3","pages":"C3-C3"},"PeriodicalIF":1.9,"publicationDate":"2025-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10930342","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143637857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this article, we mainly report the radiation response of n-channel depletion-mode gallium arsenide (GaAs) metal-semiconductor field-effect transistors (MESFETs) under heavy ion, proton, and electron irradiation. The maximum transconductance (${G} _{text {MAX}}$ ) and drain saturation current (${I} _{text {DSS}}$ ), which can reflect the carrier removal and mobility degradation induced by displacement damage, are selected as evaluation indicators, and two kinds of damage factors are derived: ${K} _{G}$ and ${K} _{I}$ . The nonionizing energy loss (NIEL) of different particles deposited in the epitaxial channel layer of GaAs MESFETs is calculated and used to correlate ${K} _{G}$ and ${K} _{I}$ , respectively. The good linear relationship between damage factors and NIEL makes it possible to predict the degradation of ${G} _{text {MAX}}$ and ${I} _{text {DSS}}$ . On this basis, two semiempirical damage equations describing GaAs MESFETs displacement damage are derived and verified by 27-MeV F. We also derive the damage coefficient “$gamma $ ” in the more general damage equation, which has a value of $5.5times 10^{-13}$ g/MeV for ${G} _{text {MAX}}$ and $8.9times 10^{-13}$ g/MeV for ${I} _{text {DSS}}$ . Besides, MESFETs made from other materials may also align with the damage equation. A single irradiation experiment can determine the damage coefficient $gamma $ values in principle. This work extends the application of the NIEL-based displacement damage dose (DDD) method in GaAs MESFETs.
{"title":"Displacement Damage Correlation of Heavy Ion, Proton, and Electron Irradiation in GaAs MESFETs","authors":"Shuhao Hou;Shangli Dong;Jianqun Yang;Zhongli Liu;Enhao Guan;Gang Lin;Guojian Shao;Yubao Zhang;Jicheng Jiang;Xingji Li","doi":"10.1109/TNS.2025.3543451","DOIUrl":"https://doi.org/10.1109/TNS.2025.3543451","url":null,"abstract":"In this article, we mainly report the radiation response of n-channel depletion-mode gallium arsenide (GaAs) metal-semiconductor field-effect transistors (MESFETs) under heavy ion, proton, and electron irradiation. The maximum transconductance (<inline-formula> <tex-math>${G} _{text {MAX}}$ </tex-math></inline-formula>) and drain saturation current (<inline-formula> <tex-math>${I} _{text {DSS}}$ </tex-math></inline-formula>), which can reflect the carrier removal and mobility degradation induced by displacement damage, are selected as evaluation indicators, and two kinds of damage factors are derived: <inline-formula> <tex-math>${K} _{G}$ </tex-math></inline-formula> and <inline-formula> <tex-math>${K} _{I}$ </tex-math></inline-formula>. The nonionizing energy loss (NIEL) of different particles deposited in the epitaxial channel layer of GaAs MESFETs is calculated and used to correlate <inline-formula> <tex-math>${K} _{G}$ </tex-math></inline-formula> and <inline-formula> <tex-math>${K} _{I}$ </tex-math></inline-formula>, respectively. The good linear relationship between damage factors and NIEL makes it possible to predict the degradation of <inline-formula> <tex-math>${G} _{text {MAX}}$ </tex-math></inline-formula> and <inline-formula> <tex-math>${I} _{text {DSS}}$ </tex-math></inline-formula>. On this basis, two semiempirical damage equations describing GaAs MESFETs displacement damage are derived and verified by 27-MeV F. We also derive the damage coefficient “<inline-formula> <tex-math>$gamma $ </tex-math></inline-formula>” in the more general damage equation, which has a value of <inline-formula> <tex-math>$5.5times 10^{-13}$ </tex-math></inline-formula> g/MeV for <inline-formula> <tex-math>${G} _{text {MAX}}$ </tex-math></inline-formula> and <inline-formula> <tex-math>$8.9times 10^{-13}$ </tex-math></inline-formula> g/MeV for <inline-formula> <tex-math>${I} _{text {DSS}}$ </tex-math></inline-formula>. Besides, MESFETs made from other materials may also align with the damage equation. A single irradiation experiment can determine the damage coefficient <inline-formula> <tex-math>$gamma $ </tex-math></inline-formula> values in principle. This work extends the application of the NIEL-based displacement damage dose (DDD) method in GaAs MESFETs.","PeriodicalId":13406,"journal":{"name":"IEEE Transactions on Nuclear Science","volume":"72 3","pages":"858-865"},"PeriodicalIF":1.9,"publicationDate":"2025-02-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143638003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-17DOI: 10.1109/TNS.2025.3539562
{"title":"IEEE Transactions on Nuclear Science information for authors","authors":"","doi":"10.1109/TNS.2025.3539562","DOIUrl":"https://doi.org/10.1109/TNS.2025.3539562","url":null,"abstract":"","PeriodicalId":13406,"journal":{"name":"IEEE Transactions on Nuclear Science","volume":"72 2","pages":"C3-C3"},"PeriodicalIF":1.9,"publicationDate":"2025-02-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10891363","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143430495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This study proposes a clock synchronization protocol using the functionalities of IDELAYE2 and IOSERDESE2 primitives of an AMD Xilinx field-programmable gate array (FPGA) to serve as a general-purpose data-streaming type time-to-digital converter (TDC) for particle and nuclear physics experiments. A clock synchronization protocol called local area common clock protocol (LACCP) was developed as the upper layer protocol of a proprietary link (MIKUMARI), which was defined prior to this work by a community of users from the experimental physics field in Japan. Clock synchronization is realized using a round-trip time measurement with the system clock period and a fine offset time estimation, which corresponds to the clock signal phase difference between the primary and secondary FPGAs. The fine offset measurement is based on information from the IDELAYE2 and ISERDESE2 primitives utilized as the physical layer of the MIKUMARI link. No extra component is used. The LACCP can be implemented in an FPGA using general IO pin pairs for serial transmission and reception. A streaming high-resolution TDC (Str-HRTDC) was developed based on a tapped-delay-line (TDL) built from CARRY4 primitives in the AMD Xilinx Kintex-7 FPGA. It continuously measures the timing with 19.5-ps intrinsic resolution in $sigma $ and provides unique timestamp information over 2.4 h by introducing the time frame structure defined and synchronized by LACCP. The clock synchronization accuracy and the timing resolution were evaluated by connecting four modules with optical fibers up to 100 m in length. No cable length dependence was confirmed. The obtained synchronization accuracy was approximately 300 ps. The timing resolution between two synchronized modules was 23.1 ps in $sigma $ .
{"title":"General-Purpose Data Streaming FPGA TDC Synchronized by SerDes-Based Clock Synchronization Technique","authors":"Ryotaro Honda;Masahiro Ikeno;Che-Sheng Lin;Masayoshi Shoji","doi":"10.1109/TNS.2025.3541731","DOIUrl":"https://doi.org/10.1109/TNS.2025.3541731","url":null,"abstract":"This study proposes a clock synchronization protocol using the functionalities of IDELAYE2 and IOSERDESE2 primitives of an AMD Xilinx field-programmable gate array (FPGA) to serve as a general-purpose data-streaming type time-to-digital converter (TDC) for particle and nuclear physics experiments. A clock synchronization protocol called local area common clock protocol (LACCP) was developed as the upper layer protocol of a proprietary link (MIKUMARI), which was defined prior to this work by a community of users from the experimental physics field in Japan. Clock synchronization is realized using a round-trip time measurement with the system clock period and a fine offset time estimation, which corresponds to the clock signal phase difference between the primary and secondary FPGAs. The fine offset measurement is based on information from the IDELAYE2 and ISERDESE2 primitives utilized as the physical layer of the MIKUMARI link. No extra component is used. The LACCP can be implemented in an FPGA using general IO pin pairs for serial transmission and reception. A streaming high-resolution TDC (Str-HRTDC) was developed based on a tapped-delay-line (TDL) built from CARRY4 primitives in the AMD Xilinx Kintex-7 FPGA. It continuously measures the timing with 19.5-ps intrinsic resolution in <inline-formula> <tex-math>$sigma $ </tex-math></inline-formula> and provides unique timestamp information over 2.4 h by introducing the time frame structure defined and synchronized by LACCP. The clock synchronization accuracy and the timing resolution were evaluated by connecting four modules with optical fibers up to 100 m in length. No cable length dependence was confirmed. The obtained synchronization accuracy was approximately 300 ps. The timing resolution between two synchronized modules was 23.1 ps in <inline-formula> <tex-math>$sigma $ </tex-math></inline-formula>.","PeriodicalId":13406,"journal":{"name":"IEEE Transactions on Nuclear Science","volume":"72 3","pages":"614-622"},"PeriodicalIF":1.9,"publicationDate":"2025-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143637824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This article investigates the effects of cumulative damage, specifically negative bias temperature instability (NBTI), on the transient phenomenon known as single-event burnout (SEB) in power vertical diffused metal-oxide–semiconductor field-effect transistors (VDMOSFETs). Tantalum heavy ion irradiation (THII) experiments were conducted on devices subjected to various pretreatments: negative bias temperature stress (NBTS), hydrogen, low temperature, and a combination of hydrogen and NBTS. The results indicate that devices pretreated with NBTS exhibit increased sensitivity to SEB, whereas those subjected to other pretreatment methods demonstrate decreased sensitivity. In addition, the subthreshold mid-gap technique (SMGT) was employed to differentiate between interface traps and oxide charges, with subsequent technology computer-aided design (TCAD) simulations analyzing their impacts on SEB. The findings reveal that NBTS pretreatment primarily reduces the built-in potential ($varphi _{text {B}}$ ) of parasitic bipolar junction transistor (BJT) conduction by generating oxide charges, thereby increasing SEB sensitivity. Conversely, pretreatments with hydrogen and low temperature promote the conversion of oxide charges into interface traps, resulting in decreased SEB sensitivity. Although the change in SEB sensitivity is relatively small, this research reveals a synergistic interaction between NBTI and SEB, which may lead to premature SEB occurrences and reduce the operational lifespan of power VDMOS transistors.
{"title":"Influence of Negative Bias Temperature Instability on Single-Event Burnout in n-Channel Power VDMOS Transistors","authors":"Fengkai Liu;Lei Wu;Shuo Liu;Zhijie Zhou;Yadong Wei;Kai Wang;Huimin Geng;Zhongli Liu;Jianqun Yang;Xingji Li","doi":"10.1109/TNS.2025.3541492","DOIUrl":"https://doi.org/10.1109/TNS.2025.3541492","url":null,"abstract":"This article investigates the effects of cumulative damage, specifically negative bias temperature instability (NBTI), on the transient phenomenon known as single-event burnout (SEB) in power vertical diffused metal-oxide–semiconductor field-effect transistors (VDMOSFETs). Tantalum heavy ion irradiation (THII) experiments were conducted on devices subjected to various pretreatments: negative bias temperature stress (NBTS), hydrogen, low temperature, and a combination of hydrogen and NBTS. The results indicate that devices pretreated with NBTS exhibit increased sensitivity to SEB, whereas those subjected to other pretreatment methods demonstrate decreased sensitivity. In addition, the subthreshold mid-gap technique (SMGT) was employed to differentiate between interface traps and oxide charges, with subsequent technology computer-aided design (TCAD) simulations analyzing their impacts on SEB. The findings reveal that NBTS pretreatment primarily reduces the built-in potential (<inline-formula> <tex-math>$varphi _{text {B}}$ </tex-math></inline-formula>) of parasitic bipolar junction transistor (BJT) conduction by generating oxide charges, thereby increasing SEB sensitivity. Conversely, pretreatments with hydrogen and low temperature promote the conversion of oxide charges into interface traps, resulting in decreased SEB sensitivity. Although the change in SEB sensitivity is relatively small, this research reveals a synergistic interaction between NBTI and SEB, which may lead to premature SEB occurrences and reduce the operational lifespan of power VDMOS transistors.","PeriodicalId":13406,"journal":{"name":"IEEE Transactions on Nuclear Science","volume":"72 3","pages":"901-907"},"PeriodicalIF":1.9,"publicationDate":"2025-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143637942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-07DOI: 10.1109/TNS.2025.3539695
Charu Sharma;Tanmoy Biswas;R. P. Behera;S. Amirthapandian
Neutron irradiation testing is becoming important for commercial-off-the-shelf (COTS) devices of the instrument and control (I&C) system while working in extreme environment applications where the risk of radiation is constant. This study exposes AT89C51RD2 8-bit high-performance flash microcontrollers by varying neutron fluence, assessing their resilience and vulnerabilities through in situ and ex situ experiments. Radiation tests were conducted with thermal and epithermal neutrons. Our results emphasize the importance of shielding, which shows greater resilience of the device in prolonging device lifespan, exhibiting fewer single-event upsets (SEUs) and better reliability in radiation-exposed environments. A single-event functional interrupt (SEFI) was observed during both in situ and ex situ experiments. During in situ experiments (thermal neutron irradiation), the failure was observed when the damage was ~10-8–10-7 dpa, whereas, during ex situ experiments (thermal and epithermal neutron irradiation), the performance of the microcontroller was affected when the damage is ~10-2 dpa. The reason for failure in the device could be due to damage produced by gamma rays (produced by induced activity) and displacement damage [by recoil and primary knock-on atoms (PKAs)]. The presence of 10B in the device, along with interactions with high-energy neutrons, can also lead to functional failures. However, overall findings suggest the potential for the device to develop robust systems in high-radiation environments, as it demonstrates the ability to withstand high neutron flux.
{"title":"Investigations on the Effects of Neutron Irradiation on the Commercial 8051 Microcontroller","authors":"Charu Sharma;Tanmoy Biswas;R. P. Behera;S. Amirthapandian","doi":"10.1109/TNS.2025.3539695","DOIUrl":"https://doi.org/10.1109/TNS.2025.3539695","url":null,"abstract":"Neutron irradiation testing is becoming important for commercial-off-the-shelf (COTS) devices of the instrument and control (I&C) system while working in extreme environment applications where the risk of radiation is constant. This study exposes AT89C51RD2 8-bit high-performance flash microcontrollers by varying neutron fluence, assessing their resilience and vulnerabilities through in situ and ex situ experiments. Radiation tests were conducted with thermal and epithermal neutrons. Our results emphasize the importance of shielding, which shows greater resilience of the device in prolonging device lifespan, exhibiting fewer single-event upsets (SEUs) and better reliability in radiation-exposed environments. A single-event functional interrupt (SEFI) was observed during both in situ and ex situ experiments. During in situ experiments (thermal neutron irradiation), the failure was observed when the damage was ~10-8–10-7 dpa, whereas, during ex situ experiments (thermal and epithermal neutron irradiation), the performance of the microcontroller was affected when the damage is ~10-2 dpa. The reason for failure in the device could be due to damage produced by gamma rays (produced by induced activity) and displacement damage [by recoil and primary knock-on atoms (PKAs)]. The presence of 10B in the device, along with interactions with high-energy neutrons, can also lead to functional failures. However, overall findings suggest the potential for the device to develop robust systems in high-radiation environments, as it demonstrates the ability to withstand high neutron flux.","PeriodicalId":13406,"journal":{"name":"IEEE Transactions on Nuclear Science","volume":"72 3","pages":"848-857"},"PeriodicalIF":1.9,"publicationDate":"2025-02-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143637788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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