Cross-Chip Partial Reconfiguration for the Initialization of Modular and Scalable Heterogeneous Systems

Abstract

The almost unlimited possibilities to customize the logic in a field-programmable gate array (FPGA) is one of the main reasons for the versatility of these devices. Partial reconfiguration exploits this capability even further by allowing to replace logic in predefined FPGA regions at runtime. This is especially relevant in heterogeneous system-on-chip (SoC), combining FPGA fabric with conventional processors on a single die. Tight integration and supporting frameworks, such as the FPGA subsystem in Linux, facilitate use, for example, to dynamically load custom hardware accelerators. Although this example is one of the most common use cases for partial reconfiguration, the possible applications go far beyond. We propose to use partial reconfiguration in combination with the advanced extensible interface (AXI) Chip2Chip (c2c) cross-chip bus to extend the resources of heterogeneous multiprocessor SoC (MPSoC) and radio-frequency SoC (RFSoC) devices by connecting peripheral FPGAs. With AXI C2C, it is easily possible to link the programmable logic (PL) of the individual devices, but partial reconfiguration on peripheral FPGAs utilizing the same channel is not officially supported. By using an AXI internal configuration access port (ICAP) controller in combination with custom Linux drivers, we show that it is possible to enable the processing system (PS) of the heterogeneous SoC to perform partial reconfiguration on peripheral FPGAs and, thus, to seamlessly access and manage the entire multidevice system. As a result, software and FPGA firmware updates can be applied to the entire system at runtime, and peripheral FPGAs can be added and removed during operation.