A 190-217-GHz Frequency Multiplier Chain With 13.2 dB Conversion Gain in 65-nm CMOS

Abstract

This brief presents a high gain frequency multiplier chain in 65-nm CMOS technology. The frequency doubler transistor interconnection layout is carefully designed to minimize the parasitic effect and enhance performance. The gate bias voltage is discussed and optimized to improve the doubler conversion gain. A shorting stub for the second harmonic at the gate terminal is added to enhance both the conversion gain and saturated output power. A two-stage neutralized power amplifier is designed to provide sufficient power to drive the frequency doubler. Measurement results show the chip achieves a peak conversion gain of 13.2 dB at 208 GHz with −17.6 dBm input power. The saturation output power is 0.3 dBm, while the chip still maintains an 11 dB conversion gain at 212 GHz. The 3-dB output power bandwidth is 13.2% from 190 to 217 GHz. With 100 mW DC power consumption, the peak power-added efficiency is 0.99%.