An 800-MS/s 8.2-ENOB TDC-Assisted Pipelined-SAR ADC With Parallel Conversion

Abstract

This brief presents a ring amplifier embedded with the time-to-digital converter (TDC) to implement parallel conversion techniques in a pipelined-SAR ADC. The ring amplifier, functioning as the residue amplifier, has a crucial role of providing information for the time-domain quantizer. This technique need no additional complex circuits and capacitors for applying parallel conversion techniques, resulting in 20% sampling rate boost. Fabricated in a 28-nm CMOS technology, the ADC achieves a 45.06-dB SNDR at 800 MS/s and consumes 4.84 mW with a 0.9-V supply, yielding a Walden FOM of 41.4 fJ/conv-step.