Ultra-Low-Power High PSRR Sub-1 V Voltage Reference Circuit in 22 nm FDSOI CMOS

Abstract

This brief presents an ultra-low-power sub-1V voltage reference circuit using a self-cascode technique to improve power supply rejection ratio (PSRR) for battery-powered applications. The proposed voltage reference circuit has been fabricated in 22 nm fully-depleted silicon-on-insulator (FDSOI) CMOS technology, and it occupies an active area of 0.0104 $\text {mm}^{{2}}$ . The measured average output voltage $\text {V}_{\text {REF}}$ from 12 samples at room temperature is 598 mV with a standard deviation of 0.37%. The $\text {V}_{\text {REF}}$ shows measured average temperature coefficient $\text {TC}_{\text {avg}}$ of 61 $\text {ppm/}^{\circ }\text {C}$ over the temperature range of −40°C to 120°C, line sensitivity of 0.12%/V from 1.2V to 1.8V supply voltages, and measured PSRR of 66 dB at 10 Hz. A total power consumption is 45.6nW from a 1.2V supply voltage.