A Post-Bond ILV Test Method in Monolithic 3-D ICs

Abstract

Monolithic 3-D (M3D) integrated circuits (ICs) have the potential to achieve significantly higher device density compared with conventional ICs. The implementation of nanoscale interlayer vias (ILVs) in M3D plays a pivotal role in achieving enhanced transistor density and increased flexibility for circuit design. However, the high integration density and aggressive scaling of the interlayer dielectric make ILVs especially prone to defects. In this article, we propose a post-bond ILV test method for the detection and diagnosis of ILVs’ open faults, stuck-at faults (SAFs), and short faults in the fabrication process of M3D ICs. The proposed method is well-suited for post-bond ILV test, which can significantly save the cost and improve the yield. The HSPICE simulation results demonstrate that the proposed method can effectively detect and localize ILVs’ open, stuck-at 0, stuck-at 1, and short faults. Evaluation results for M3D benchmarks demonstrate the proposed method has a quite small power-performance–area (PPA) overhead and a relatively low test-time overhead.