Power-Efficient Analog Hardware Architecture of the Learning Vector Quantization Algorithm for Brain Tumor Classification

IF 2.8 2区 工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-08-30 DOI:10.1109/TVLSI.2024.3447903
Vassilis Alimisis;Emmanouil Anastasios Serlis;Andreas Papathanasiou;Nikolaos P. Eleftheriou;Paul P. Sotiriadis
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Abstract

This study introduces a design methodology pertaining to analog hardware architecture for the implementation of the learning vector quantization (LVQ) algorithm. It consists of three main approaches that are separated based on the distance calculation circuit (DCC) and, more specifically; Euclidean distance, Sigmoid function, and Squarer circuits. The main building blocks of each approach are the DCC and the current comparator (CC). The operational principles of the architecture are extensively elucidated and put into practice through a power-efficient configuration (operating less than 650 nW) within a low-voltage setup (0.6 V). Each specific implementation is tested on a brain tumor classification task achieving more than 96.00% classification accuracy. The designs are realized using a 90-nm CMOS process and developed utilizing the Cadence IC Suite for both schematic and physical design. Through a comparative analysis of postlayout simulation outcomes with an equivalent software-based classifier and related works, the accuracy of the applied modeling and design methodologies is validated.
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用于脑肿瘤分类的学习矢量量化算法的高能效模拟硬件架构
本研究介绍了实现学习矢量量化(LVQ)算法的模拟硬件架构设计方法。它包括基于距离计算电路 (DCC) 的三种主要方法,更具体地说,包括欧氏距离、西格莫函数和 Squarer 电路。每种方法的主要构件是 DCC 和电流比较器 (CC)。通过低电压设置(0.6 V)中的高能效配置(运行功耗小于 650 nW),该架构的运行原理得到了广泛阐释并付诸实践。每个具体实现都在脑肿瘤分类任务中进行了测试,分类准确率超过 96.00%。这些设计采用 90 纳米 CMOS 工艺实现,并利用 Cadence IC Suite 进行原理图和物理设计。通过将布局后仿真结果与基于软件的等效分类器和相关作品进行比较分析,验证了应用建模和设计方法的准确性。
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来源期刊
CiteScore
6.40
自引率
7.10%
发文量
187
审稿时长
3.6 months
期刊介绍: The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.
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