A 65 nm CMOS Analog Programmable Standard Cell Library for Mixed-Signal Computing

IF 2.8 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-08-19 DOI:10.1109/TVLSI.2024.3432916

Pranav O. Mathews;Praveen Raj Ayyappan;Afolabi Ige;Swagat Bhattacharyya;Linhao Yang;Jennifer O. Hasler

引用次数: 0

Abstract

Integrated circuit (IC) design for analog computing requires similar toolflows and synthesis as large-scale digital systems, in-turn necessitating a library of general-purpose analog cells. To this end, we present a programmable, floating-gate (FG)-based analog standard cell library in a commercially available 65 nm process that allows analog IC designers to use synthesis tools with an abstracted design mindset similar to large-scale digital design. We fabricate the test cells, which include filters with programmable corners, an analog classifier, and an arbitrary waveform generator (AWG); experimentally characterize FG programming; and experimentally demonstrate the performance of the standard cells. Overall, the standard cells achieve a similar or smaller footprint than previous approaches while leveraging the benefits of FG programming at smaller technology nodes.

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用于混合信号计算的 65 纳米 CMOS 模拟可编程标准单元库

模拟计算的集成电路 (IC) 设计需要与大规模数字系统类似的工具流程和综合，因此需要一个通用模拟单元库。为此，我们在商用 65 纳米工艺中推出了基于浮栅 (FG) 的可编程模拟标准单元库，使模拟集成电路设计人员能够以类似于大规模数字设计的抽象设计思路使用综合工具。我们制作了测试单元，其中包括具有可编程拐角的滤波器、模拟分类器和任意波形发生器 (AWG)；通过实验鉴定了 FG 编程；并通过实验演示了标准单元的性能。总体而言，标准单元实现了与以往方法相似或更小的占位面积，同时在更小的技术节点上充分利用了 FG 编程的优势。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.

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