Co-Design of Inter-Chiplet, Package, and System Interconnect Protocols

IF 2.8 3区 计算机科学 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Micro Pub Date : 2024-08-26 DOI:10.1109/mm.2024.3447711
Tony Chan Carusone, Dustin Dunwell, Sundeep Gupta, Letizia Giuliano, Adrien Auge, Michael Klempa, Sue Hung Fung
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来源期刊
IEEE Micro
IEEE Micro 工程技术-计算机:软件工程
CiteScore
7.50
自引率
0.00%
发文量
164
审稿时长
>12 weeks
期刊介绍: IEEE Micro addresses users and designers of microprocessors and microprocessor systems, including managers, engineers, consultants, educators, and students involved with computers and peripherals, components and subassemblies, communications, instrumentation and control equipment, and guidance systems. Contributions should relate to the design, performance, or application of microprocessors and microcomputers. Tutorials, review papers, and discussions are also welcome. Sample topic areas include architecture, communications, data acquisition, control, hardware and software design/implementation, algorithms (including program listings), digital signal processing, microprocessor support hardware, operating systems, computer aided design, languages, application software, and development systems.
期刊最新文献
Interconnect Design for Heterogeneous Integration of Chiplets in the AMD Instinct™ MI300X Accelerator ReDL: A Hybrid Memory System with Scalable Data Management Strategies for DNN Applications UCIe: Standard for an Open Chiplet Ecosystem Energy-Efficient Parallel Interconnects for Chiplet Integration Co-Design of Inter-Chiplet, Package, and System Interconnect Protocols
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