Statistical Analysis of Increased Immunity to Poly-Si Grain Boundaries in Nanosheet CMOS Logic Inverter Through Sheet Stacking

Abstract

Herein, the advantages of sheet stacking in polycrystalline Si (Poly-Si)–based nanosheet MOSFETs and CMOS inverters were statistically analyzed through technology computer-aided design simulations. Poly-Si is used as the channel material to make the high-density three-dimensional structure in a simple process. We studied the transfer characteristics of single-layer nanosheet (SN) MOSFETs and 3-layer multi-bridge nanosheet (MN) MOSFETs depending on the location and the number of grain boundaries (GBs). Further, the DC/switching performance of SN CMOS and MN CMOS inverters was analyzed based on the location and number of GBs. The multilayer stacked structure not only increased the average on state current and switching speed but also reduced the dispersion of characteristics and performance. In addition, multilayer stacked structure increased the yield based on the 3 sigma-level. Therefore, the stacked MN structure is suitable for implementation in MOSFETs and CMOS inverters with high performance and reliability against fluctuations caused by poly-Si GBs.