Design and Optimization of Ferroelectric Spacer Engineered Modified Bi-Level Negative Capacitance FET: An Analog/RF Evaluation Perspective

Abstract

This study for the first time uses a 3 nm technology node (N3) bi-level negative capacitance FET (BLNC-FET) to examine the influence of symmetric underlap ferroelectric dual-k spacer with raised source/drain on dc and analog/RF performance. The prior dc analysis reveals the fact that BLNC-FET has an edge over the conventional and BL device. Moreover, the proposed device shows an enhancement of 7.2% in ${I}_{\text {ON}}$ (ON current), 73.58% in ${I}_{\text {OFF}}$ (OFF current), an excellent subthreshold slope (SS) of 57.51 mV/dec, and a Barrier rising of 52.75% in comparison to the Bi-Level FET. Therefore, the analysis for spacer variation ends up with an optimized dimension with high-k spacer length of 5 nm and low-k spacer length of 15 nm. Henceforth, continuing with BLNC-FET, this work proposes six different spacer placement configurations with symmetric underlap ferroelectric dual-k spacer along with a raised source/drain. Improved performance is acknowledged in terms of increased ON-current, reduced negative differential resistance (NDR), improved SS, improved ${I}_{\text {ON}}$ / ${I}_{\text {OFF}}$ ratio, and so forth. This work discovers the best results by positioning symmetric underlap dual ferroelectric dual-k spacer materials, with mitigation of NDR in DKSP1 to DKSP6. Out of all the spacer configurations, DKSP6 shows an improvement of 76.26%, 76.19%, 319%, and 317% for ${I}_{\text {ON}}$ , SS, ${g}_{m}$ (transconductance), and transconductance generation factor (TGF), respectively, and the presence of positive DIBL and absence of NDR makes DKSP6 the better choice for BLNC-FET. It also analyzes the proposed device performance at the circuit level designing a CMOS inverter and five-stage ring oscillator followed by noise margin (NM) calculation.