{"title":"Directly Coupled Hydrogenated Diamond FET Logic Circuit With High Voltage Gain","authors":"Yuesong Liang;Wei Wang;Fang Lin;Tianlin Niu;Genqiang Chen;Fei Wang;Qi Li;Shi He;Minghui Zhang;Yanfeng Wang;Feng Wen;Hong-Xing Wang","doi":"10.1109/LED.2024.3448363","DOIUrl":null,"url":null,"abstract":"The directly coupled hydrogen-terminated diamond FET logic (DCHDFL) circuit is fabricated. The E-mode and D-mode FETs are assigned as driver and load devices of the DCHDFL circuit to achieve inversion characteristics. The E-mode FET showcases high I\n<sub>DSmax</sub>\n of 53.3mA/mm, V\n<sub>TH</sub>\n of -0.8 V, low SS of 98 mV/dec and on/off ratio of 10\n<sup>9</sup>\n, which enable input/output logic level matching with a low drive/load ratio of 1.0. The peak gain of circuit increases from 12.57 to 36.3 V/V with V\n<sub>DD</sub>\n ranging from -5 V to -25 V, which is the highest gain achieved of diamond inverters, due to the high on/off ratio and low SS of E-mode FET. This circuit exhibits proper functions up to 200 °C, demonstrating a good thermal stability. These results indicate the great potential and possibilities for diamond smart power integrated circuit application.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"45 10","pages":"1698-1701"},"PeriodicalIF":4.1000,"publicationDate":"2024-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Electron Device Letters","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10644005/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
The directly coupled hydrogen-terminated diamond FET logic (DCHDFL) circuit is fabricated. The E-mode and D-mode FETs are assigned as driver and load devices of the DCHDFL circuit to achieve inversion characteristics. The E-mode FET showcases high I
DSmax
of 53.3mA/mm, V
TH
of -0.8 V, low SS of 98 mV/dec and on/off ratio of 10
9
, which enable input/output logic level matching with a low drive/load ratio of 1.0. The peak gain of circuit increases from 12.57 to 36.3 V/V with V
DD
ranging from -5 V to -25 V, which is the highest gain achieved of diamond inverters, due to the high on/off ratio and low SS of E-mode FET. This circuit exhibits proper functions up to 200 °C, demonstrating a good thermal stability. These results indicate the great potential and possibilities for diamond smart power integrated circuit application.
期刊介绍：
IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanoelectronics, optoelectronics, photovoltaics, power ICs and micro-sensors.
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