A 2048×60m4 SRAM Design in Intel 4 With Around-the-Array Power Delivery Scheme Using PowerVia

Abstract

A $2048\times 60$ m4 SRAM design in Intel 4 using PowerVia is presented. Instead of integrating PowerVia directly into bitcell, an around-the-array power-delivery scheme is introduced to limit the area increase of an SRAM bitcell array, while utilizing the benefits of PowerVias in logic peripheral circuits. The measured test chip demonstrates an improved or comparable $\rm V_{MIN}$ and performance compared to similar nonPowerVia designs. An 8.3-Mb macro comprising of HCC bitcell-based $2048\times 60$ m4 instance is 2% smaller than similar nonPowerVia design and shows a clean voltage-frequency Shmoo.