{"title":"A novel nanoscale FD-SOI MOSFET with energy barrier and heat-sink engineering for enhanced electric field uniformity","authors":"","doi":"10.1016/j.micrna.2024.207986","DOIUrl":null,"url":null,"abstract":"<div><p>This paper aims to present a novel method to mitigate the undesirable issues associated with short-channel-effects (SCEs) and the critical lattice temperature of a fully depleted silicon-on-insulator (FD-SOI) MOSFET in the nanoscale regime. The proposed approach is based on simultaneously merging the energy barrier and heat-sink engineering simultaneously. Hafnium oxide as a high-k dielectric inside the channel region around the drain region is embedded to redistribute the band energy resulting in the enhancement of the energy barrier. This reformation of the band profile reduces variations in the channel depletion charge volume percentage caused by the drain voltage, thereby mitigating short-channel effects (SCEs). In order to promote effective thermal conduction, a portion of the buried oxide is replaced by doped P-type silicon which acts as an effective heat-sink. The devices under the investigation have been simulated using SILVACO software, considering the comprehensive physical models. Drain-Induced Barrier Lowering (DIBL), leakage current, I<sub>on</sub> to I<sub>off</sub> ratio, subthreshold swing, hot carrier effect and lattice temperature as the essential parameters have been successfully improved for the proposed device in comparison to the conventional device.</p></div>","PeriodicalId":100923,"journal":{"name":"Micro and Nanostructures","volume":null,"pages":null},"PeriodicalIF":2.7000,"publicationDate":"2024-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Micro and Nanostructures","FirstCategoryId":"1085","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S2773012324002358","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"PHYSICS, CONDENSED MATTER","Score":null,"Total":0}
引用次数: 0
Abstract
This paper aims to present a novel method to mitigate the undesirable issues associated with short-channel-effects (SCEs) and the critical lattice temperature of a fully depleted silicon-on-insulator (FD-SOI) MOSFET in the nanoscale regime. The proposed approach is based on simultaneously merging the energy barrier and heat-sink engineering simultaneously. Hafnium oxide as a high-k dielectric inside the channel region around the drain region is embedded to redistribute the band energy resulting in the enhancement of the energy barrier. This reformation of the band profile reduces variations in the channel depletion charge volume percentage caused by the drain voltage, thereby mitigating short-channel effects (SCEs). In order to promote effective thermal conduction, a portion of the buried oxide is replaced by doped P-type silicon which acts as an effective heat-sink. The devices under the investigation have been simulated using SILVACO software, considering the comprehensive physical models. Drain-Induced Barrier Lowering (DIBL), leakage current, Ion to Ioff ratio, subthreshold swing, hot carrier effect and lattice temperature as the essential parameters have been successfully improved for the proposed device in comparison to the conventional device.
本文旨在提出一种新方法,以缓解与短沟道效应(SCE)和纳米级全耗尽型硅绝缘体(FD-SOI)MOSFET 的临界晶格温度相关的不良问题。所提出的方法基于同时合并能量势垒和散热工程。在漏极区周围的沟道内嵌入氧化铪作为高 K 电介质,以重新分配带能,从而增强能垒。这种对能带剖面的改革减少了漏极电压引起的沟道耗尽电荷量百分比的变化,从而减轻了短沟道效应(SCE)。为了促进有效的热传导,部分埋藏的氧化物被掺杂的 P 型硅取代,从而起到了有效的散热作用。考虑到全面的物理模型,我们使用 SILVACO 软件对研究中的器件进行了模拟。与传统器件相比,拟议器件的漏极诱导势垒降低 (DIBL)、漏电流、离子与离子关断比、亚阈值摆动、热载流子效应和晶格温度等基本参数都得到了成功改善。