Assessment of Trap Charges for Analog/RF FOMs and Linearity Behaviour on InAs Based Dual Metal Hetero Gate Oxide TFET for Enhanced Reliability

IF 2.8 3区 材料科学 Q3 CHEMISTRY, PHYSICAL Silicon Pub Date : 2024-09-17 DOI:10.1007/s12633-024-03137-y
Vedvrat
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Abstract

The aim of this study is to examine a low-power, InAs/Si hetero-gate oxide double-gate Tunnel field effect transistor (H-DM-DG-InAs-TFET) for high frequency application and to determine how trap charges (ITCs) affect the DC characteristics and analog/RF electrical performance metrics of the device. It is unfeasible to disregard the trap charges because the device's performance and reliability are negatively impacted by the buildup of trap charges at the interface between the semiconductor and oxide. Hence, an in-depth analysis of the performance characteristics of the proposed device, a InAs/Si hetero-gate oxide double-gate Tunnel FET (H-DM-DG-InAs-TFET), is conducted in this work to ascertain the impact of interface trap charges (ITCs). Comparison study of proposed device with dual metal gate Si Tunnel Field Effect Transistor (DM-DG-Si-TFET) is conducted. The proposed device is capable of effortlessly carrying enhanced ON current (1.54 × 10–3 A/µm) and exhibits improved current ratio (1.63 × 1011). To ascertain the device's suitability for low-power applications, its threshold voltage is determined by employing a constant current methodology. An improvement in threshold voltage (0.17 V) is noted. According to the study, the efficacy of the proposed device was enhanced due to the dielectric engineering performed on the oxide layer. Further investigation is conducted into the impact of ITCs on linearity parameters, as advanced communication device necessitates linear responses. The comparison with the DM-DG-Si-TFET reveals that the proposed TFET has virtually no distortion and a negligible impact on the linearity metrics. This indicates that the proposed TFET can be utilised in extremely low-power, high-frequency electrical devices.

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评估模拟/射频 FOM 的陷波电荷以及基于 InAs 的双金属异质栅极氧化物 TFET 的线性行为,以提高可靠性
本研究的目的是检验一种用于高频应用的低功耗 InAs/Si 异质栅氧化物双栅隧道场效应晶体管 (H-DM-DG-InAs-TFET),并确定陷阱电荷 (ITC) 如何影响器件的直流特性和模拟/射频电气性能指标。不考虑阱电荷是不可行的,因为半导体和氧化物之间的界面上积累的阱电荷会对器件的性能和可靠性产生负面影响。因此,本研究对所提出的 InAs/Si 异质栅氧化物双栅隧道场效应晶体管(H-DM-DG-InAs-TFET)的性能特性进行了深入分析,以确定界面陷阱电荷(ITC)的影响。还对所提出的器件与双金属栅硅隧道场效应晶体管(DM-DG-Si-TFET)进行了比较研究。所提出的器件能够毫不费力地承载更强的导通电流(1.54 × 10-3 A/µm),并显示出更高的电流比(1.63 × 1011)。为确定该器件是否适用于低功耗应用,采用恒流方法确定了其阈值电压。结果表明,阈值电压有所提高(0.17 V)。研究结果表明,由于在氧化层上实施了介电工程,该器件的功效得到了提高。由于先进的通信设备需要线性响应,因此进一步研究了 ITC 对线性参数的影响。与 DM-DG-Si-TFET 的比较显示,所提出的 TFET 几乎没有失真,对线性度指标的影响可以忽略不计。这表明拟议的 TFET 可用于极低功耗、高频率的电子设备。
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来源期刊
Silicon
Silicon CHEMISTRY, PHYSICAL-MATERIALS SCIENCE, MULTIDISCIPLINARY
CiteScore
5.90
自引率
20.60%
发文量
685
审稿时长
>12 weeks
期刊介绍: The journal Silicon is intended to serve all those involved in studying the role of silicon as an enabling element in materials science. There are no restrictions on disciplinary boundaries provided the focus is on silicon-based materials or adds significantly to the understanding of such materials. Accordingly, such contributions are welcome in the areas of inorganic and organic chemistry, physics, biology, engineering, nanoscience, environmental science, electronics and optoelectronics, and modeling and theory. Relevant silicon-based materials include, but are not limited to, semiconductors, polymers, composites, ceramics, glasses, coatings, resins, composites, small molecules, and thin films.
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