An Adaptive 56-Gb/s Duo-PAM4 Detector Using Reduced Branch Maximum Likelihood Sequence Detection in a 28-nm CMOS Wireline Receiver

Abstract

This paper describes an adaptive duo-binary four-level pulse amplitude modulation (Duo-PAM4) detector that significantly reduces the bit error rate (BER) of the conventional wireline transceivers under high insertion loss (IL) channels. The parallel maximum likelihood sequence detection (MLSD) combined with parallel feed-forward equalization (FFE) is proposed to generate, equalize, and detect Duo-PAM4 signals, thus reducing BER compared to conventional decision feedback equalizer (DFE) and slicers. The proposed reduced branch MLSD reduces power consumption compared to MLSD. An improved delay zero-forcing algorithm for Duo-PAM4 is proposed to achieve fast convergence of the FFE tap coefficients, reducing convergence time by up to 72.5% compared to conventional ZF algorithms for Duo-PAM4. Both the proposed and conventional detectors are implemented in a 28-nm CMOS process at 56 Gb/s and 38-dB insertion loss. The FFE+MLSD and FFE+RB-MLSD reduce the BER by two orders of magnitude compared to conventional FFE+DFE+slicer. The RB-MLSD reduces power consumption by 21.1% compared to conventional MLSD. The detector can be easily migrated to 112Gb/s or 224Gb/s transceivers.