Analysis and Design of Wideband Active Single-Sideband Time Modulator in 0.13- μm CMOS

Abstract

A wideband active single-sideband time modulator (STM) is proposed in this paper, which achieves high-resolution frequency-independent phase shifting performance through high-precision time delay, eliminating the need for calibrations. The analysis starts with N-step time modulation sequences for the active STM, followed by discussions on enhancing the sideband suppression ratio (SSR) and the effects of quadrature mismatch on SSR. The proposed active STM is based on a periodically controlled active vector modulator with regularly scalable gate-widths, and its timing sequences for control bits feature identical duty cycles and modulation frequency ( $f_{\mathrm {P}}$ ). For verification, a wideband active STM is implemented using 0.13- $\mu $ m CMOS technology, which is composed of an input balun and quadrature generator, a periodically controlled 4-bit active vector modulator and a variable-gain stage. Measurement results indicate root mean square (RMS) phase and gain errors ranging from 0.1 to 0.4° and less than 0.2 dB respectively, within a 3-dB frequency range of 13.0 to 20.6 GHz at the maximum gain state. The active STM provides a peak gain of −0.1 dB, an equivalent 10-bit phase control across a 360° range, and a 3-bit gain control spanning 21.0 dB. The measured SSR is below −23.3 dBc, and the instantaneous bandwidth is expanded to $16f_{\mathrm {P}}$ . Additionally, the input 1-dB compression point (IP $_{\mathrm {1dB}}$ ) ranges from 6.1 to 9.3 dBm. The chip occupies a 2.4 mm2 area and consumes 58.8 mW from a 1.2 V supply voltage.