Automated Topology Synthesis of Analog Integrated Circuits With Frequency Compensation

Abstract

Analog circuit topology synthesis suffers from weak synthesis capability and low-synthesis efficiency, which result in a bottleneck toward its practical industrial applications. This article presents a proximal-policy-optimization-based circuit topology synthesis framework, which features a superior convergence rate. To further promote its synthesis efficiency, we have improved a deterministic optimization method by incorporating a bias-aware scheme and group concept, which is applied as a filter to eliminate the undesirable topologies in the early evaluation stage. Moreover, a graph-based refinement scheme is proposed to perform deterministically on the generated circuit topologies, which can efficiently add frequency compensation circuits. Compared with the state-of-the-art approaches, our proposed method not only boosts the synthesis efficiency by at least 3 times but also enhances the synthesis capability with a deterministic compensation scheme, showcasing significant advancement of performance efficacy.