A 10-Bit 500-MS/s Pipelined SAR ADC With Nonlinearity-Compensated Open-Loop Amplifier and Parallel Conversion Through Comparator Reusing

Abstract

This brief presents a 10-bit, 500-MS/s pipelined SAR ADC in 65-nm CMOS, in which both the 1st-stage and 2nd-stage employ a high-speed loop-unrolled structure to resolve 4 bits and 7 bits, respectively, with 1-bit redundancy. To speed up conversion further, the 2nd-stage’s MSB is resolved in parallel with residue amplification through reusing the 3 MSB comparators of the 1st-stage via voting, thereby reducing the 2nd-stage’s conversion time and relaxing the comparator noise requirement. The LSB of the 2nd-stage is also obtained by reusing the 3 MSB comparators of the 2nd-stage through voting. The proposed 2-stage open-loop residue amplifier achieves nonlinearity compensation through a source-follower-based CMFB circuit. With 5.1-mW power consumption, the measured SNDR and SFDR of the prototype ADC are 55.98 dB and 71.8 dB, respectively, for a near-Nyquist input frequency.