Investigation and analysis of design techniques for ultra-wideband CMOS on-chip dipole antennas for 6G sub-THz applications

Abstract

This article explores different techniques to improve the impedance bandwidth of on-chip dipole antennas in the sub-THz frequency range. Increasing the area of the dipole antenna has shown considerable improvement in bandwidth. However, this violates the design rule checks (DRC) of the foundry. Various topologies, such as squared-slotted dipole, meandered-slotted dipole, and straight-slotted dipole antennas, are introduced and implemented to increase the width of the on-chip antennas and thus the impedance bandwidth while meeting the DRC rules. All three topologies show better performance in terms of providing improved bandwidth. The straight-slotted technique is adopted as it offers less complexity and flexibility. The behavior of the impedances for different widths implemented by the straight-slotted topology has been analyzed in detail. A 6-strip straight-slotted dipole antenna results in an ultra-wide impedance bandwidth ranging from 76–262 GHz with a fractional bandwidth of 110% and a gain of −0.6 dBi at 159 GHz, while occupying a small silicon area of $567\mu m\times 112\mu m$. To the best of the authors’ knowledge, this is the highest fractional bandwidth that is reported to date at these frequencies.