Jieun Park;Yong Ki Lee;Karpinskyy Bohdan;Yunhyeok Choi;Jonghoon Shin;Hyo-Gyuem Rhew;Jongshin Shin
{"title":"A PVT-Tolerant STR-Based TRNG in 4-nm Achieving 60 Mbp/s and Its Performance Analysis via Mathematical Modeling","authors":"Jieun Park;Yong Ki Lee;Karpinskyy Bohdan;Yunhyeok Choi;Jonghoon Shin;Hyo-Gyuem Rhew;Jongshin Shin","doi":"10.1109/LSSC.2024.3419722","DOIUrl":null,"url":null,"abstract":"This letter presents a high-performance true random number generator (TRNG) based on self-timed ring (STR), showing robust tolerance to PVT variations. The evaluations were performed over 320 chips (64 chips per process corner of nn, ff, ss, sf, and fs) across three voltages (0.75 V, 0.75 V±10%) and three temperatures (\n<inline-formula> <tex-math>$- 40~^{\\circ }$ </tex-math></inline-formula>\nC, \n<inline-formula> <tex-math>$25~^{\\circ }$ </tex-math></inline-formula>\nC, and \n<inline-formula> <tex-math>$150~^{\\circ }$ </tex-math></inline-formula>\nC). All 320 test chips demonstrated stable random generation at 60 Mb/s over all the test combinations without a single failure. The verification utilized a TRNG BIST, ensuring a minimum of 0.5 min-entropy per bit. Moreover, a mathematical model for the proposed TRNG is developed to derive the throughput and the entropy of the random output.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"255-258"},"PeriodicalIF":2.2000,"publicationDate":"2024-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Solid-State Circuits Letters","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/10572268/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
Abstract
This letter presents a high-performance true random number generator (TRNG) based on self-timed ring (STR), showing robust tolerance to PVT variations. The evaluations were performed over 320 chips (64 chips per process corner of nn, ff, ss, sf, and fs) across three voltages (0.75 V, 0.75 V±10%) and three temperatures (
$- 40~^{\circ }$
C,
$25~^{\circ }$
C, and
$150~^{\circ }$
C). All 320 test chips demonstrated stable random generation at 60 Mb/s over all the test combinations without a single failure. The verification utilized a TRNG BIST, ensuring a minimum of 0.5 min-entropy per bit. Moreover, a mathematical model for the proposed TRNG is developed to derive the throughput and the entropy of the random output.