A Monolithic Differential Bridged T-Coil

0 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE microwave and wireless technology letters Pub Date : 2024-08-12 DOI:10.1109/LMWT.2024.3436613

Giovanni Scarlato;John R. Long

引用次数: 0

Abstract

Two-pole and three-pole fully differential bridged T-coils applicable to wideband and high-speed integrated circuits are described. T-coil prototypes designed for maximally flat amplitude (MFA) and envelope delay (MFED) responses are characterized. Measured transimpedance bandwidth and group delay of the two-pole MFA design are 43.2 GHz and

$7~{\pm }~2$

ps, respectively, across 45 GHz. The three-pole MFED design exhibits 23-GHz bandwidth and

$12~{\pm }~2$

-ps group delay across 30 GHz. The bandwidth extension ratio (BWER) compared to each respective unpeaked R-C circuit is

$2.43\times $

(MFA) and

$2.2\times $

(MFED). Implemented in 22-nm FD-SOI CMOS technology, the T-coil prototypes occupy a chip area of

$224 \times 215~{\mu {\text {m}}^{2}}$

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

单片差分桥接 T 型线圈

介绍了适用于宽带和高速集成电路的两极和三极全差分桥式 T 型线圈。对为最大平坦振幅（MFA）和包络延迟（MFED）响应而设计的 T 型线圈原型进行了鉴定。两极 MFA 设计的测量跨导带宽和群延迟分别为 43.2 GHz 和 $7~{\pm }~2$ ps，跨越 45 GHz。三极 MFED 设计的带宽为 23 GHz，群延迟为 12~{\pm }~2$ -ps，频率范围为 30 GHz。与各自的非尖峰 R-C 电路相比，带宽扩展比（BWER）分别为 2.43 倍（MFA）和 2.2 倍（MFED）。T 线圈原型采用 22 纳米 FD-SOI CMOS 技术，芯片面积为 224 \times 215~{\mu {text {m}}^{2}}$ 。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文去求助

来源期刊