A High-Efficiency Push–Pull Parallel-Circuit Class-E/F3 Power Amplifier for Harmonic Suppression

0 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE microwave and wireless technology letters Pub Date : 2024-08-20 DOI:10.1109/LMWT.2024.3442206

Heng Lu;Jianliang Jiang;Hengli Zhang

引用次数: 0

Abstract

In this article, a high-efficiency push-pull parallel-circuit (PC) Class-E/F3 power amplifier (PA) with a harmonic suppression network for radio frequency identification (RFID) applications is presented. With the double reactance compensation technique (D-RCT), the PA’s design of broadband performance is achieved. In addition, a low-pass (LP) Chebyshev technique is introduced to provide a simple fundamental matching network (MN). Finally, a high-efficiency push-pull PC Class-E/F3 PA is fabricated and measured. The experimental results illustrate that an output power (

${P} _{\text {out}}$

) is from 36.83 to 41.84 dBm and 82.35%–91.32% drain efficiency (DE) operating from 5 to 10.5 MHz frequency range, which agrees well with the simulation results.

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用于谐波抑制的高效推挽并联电路 E/F3 类功率放大器

本文介绍了一种带有谐波抑制网络的高效推挽并联电路（PC）E/F3 类功率放大器（PA），适用于射频识别（RFID）应用。通过双电抗补偿技术（D-RCT），实现了功率放大器的宽带性能设计。此外，还引入了低通 (LP) 切比雪夫技术，以提供一个简单的基波匹配网络 (MN)。最后，制作并测量了高效推挽式 PC Class-E/F3 功率放大器。实验结果表明，在 5 至 10.5 MHz 频率范围内，输出功率（${P} _{text {out}}$ ）为 36.83 至 41.84 dBm，漏极效率（DE）为 82.35% 至 91.32%，与仿真结果非常吻合。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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