Junha Suk;Yohan Kim;Jungho Do;Garoom Kim;Woojin Rim;Sanghoon Baek;Seiseung Yoon;Soyoung Kim
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引用次数: 0
Abstract
In this paper, we propose a process-aware analytical gate resistance model for nanosheet field-effect transistors (NSFETs). The proposed NSFET gate resistance is modeled by applying the distributed resistance coefficient, which can be used when current flows vertically and horizontally. By predicting the direction of current flow, the resistance components are approximated in series with parallel connection of divided segments. The proposed model can reflect changes in structural parameters, making it possible to predict the scaling trend of NSFETs. This is validated through TCAD simulation results. The proposed model can be implemented in general compact models such as the Berkeley short channel IGFET model (BSIM)-common multi-gate (CMG) and can be used to predict circuit performance more accurately.
期刊介绍：
The IEEE Journal of the Electron Devices Society (J-EDS) is an open-access, fully electronic scientific journal publishing papers ranging from fundamental to applied research that are scientifically rigorous and relevant to electron devices. The J-EDS publishes original and significant contributions relating to the theory, modelling, design, performance, and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanodevices, optoelectronics, photovoltaics, power IC''s, and micro-sensors. Tutorial and review papers on these subjects are, also, published. And, occasionally special issues with a collection of papers on particular areas in more depth and breadth are, also, published. J-EDS publishes all papers that are judged to be technically valid and original.
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