Scheduling of memory chips for final testing on parallel machines considering power constraints and deteriorating effects

Abstract

This paper delves into the intricate scheduling strategies crucial for the final testing phase of memory chip manufacturing within the semiconductor industry and other related sectors. It specifically addresses the complex serial-batching scheduling problem, where memory chips are tested on parallel machines under power constraints and chip deterioration effects. The processing time for each chip is significantly influenced by both the cumulative processing time of preceding chips and the power requirements for testing. We formulate this real-world optimization problem using a mixed integer nonlinear programming model. Exact solutions for small instances are obtained using a commercial solver. However, due to the model's complexity, we also develop heuristic solutions to efficiently handle larger instances. Based on the derivation of structural properties, we develop two tailored heuristic algorithms to determine the schedule for the final testing of memory chips. Additionally, we propose a refined Variable Neighborhood Search algorithm (VNS-H) that seamlessly integrates five local search strategies with two supplementary heuristic algorithms, dynamically alternating between them to ensure a balance between computational efficiency and the quality of the solutions obtained. Additionally, we establish a lower bound to validate the effectiveness of these solutions, particularly for large-scale instances. To validate the efficacy and robustness of our proposed metaheuristic algorithm, we conduct a rigorous comparison of the VNS-H algorithm with five other metaheuristic algorithms that have promising performance in various optimization problems. The results highlight the superior performance of the VNS-H algorithm. In small-scale instances, our VNS-H algorithm achieves an average makespan that is 5.52% lower compared to the original VNS. For large-scale instances, the VNS-H algorithm reduces the average makespan by 13.46% compared to VNS. Finally, we discuss the managerial implications of our findings, providing insights specifically tailored to semiconductor manufacturing enterprises based on the outcomes of this study.