A low-power common-mode insensitive rail-to-rail dynamic comparator for ADCs

Abstract

This paper presents a low-power, high-speed dynamic comparator with a rail-to-rail input common-mode ($V_{i,cm}$) range. The proposed comparator has high-speed performance throughout the 0-Vdd $V_{i,cm}$ range, thus attributing common-mode insensitivity. This work introduces a merger of NMOS and PMOS dynamic pre-amplifiers with a modified latch to achieve the rail-to-rail $V_{i,cm}$ operation. A novel activation clock logic is also proposed, activating only one pre-amplifier based on the $V_{i,cm}$ value and ensuring low-power consumption and provides reduction of 17% in the energy per conversion as compared to the comparator without activation clock logic. The proposed comparator is designed using 65-nm CMOS technology with a 1.2 V supply voltage and is operating at 1 GHz frequency. We have presented the analytical models of the delay and offset which is verified with the rigorous post-layout simulation results. To validate the robustness of the proposed comparator, the PVT corner analysis with Monte Carlo simulation is also performed for different $V_{i,cm}$.