Common Mode and Terminal Voltages With Effect of Device Junction Capacitance in Five-Level Transformerless PV Inverter

Abstract

This article presents the analysis of common mode and terminal voltages by considering the effect of device junction capacitance in single-phase dc-decoupled transformerless PV inverter configuration. The common mode and terminal voltages (CMTVs) analysis considers device junction capacitance (DJC), inverter structure, and switching pattern. The generalized expression for CMTVs is derived considering DJC, inverter structure, and switching pattern. The inverter structure and pulsewidth modulation (PWM) technique can be modified or designed to minimize or eliminate the high-frequency switching transitions using the derived generalized expression of CMTVs. This further alleviates the common mode and leakage currents flowing through the parasitic capacitance of the PV inverter system. Furthermore, an improved PWM technique is also designed for the five-level cascaded multilevel inverter, which reduces the distortions in the inverter output current apart from alleviating the leakage current. This article presents a detailed analysis for the derivation of generalized expression using the given device junction capacitance-based switching function analysis. The derived expression is further validated using simulation and experimental results.