2D Steep-Slope Tunnel Field-Effect Transistors Tuned by van der Waals Ferroelectrics

Abstract

sPower consumption has emerged as a central concern in the realm of complementary metal-oxide-semiconductor (CMOS) technology. Silicon-based semiconductor devices have now approached the fundamental thermionic limit of the subthreshold swing (SS), which is 60 mV dec⁻¹, as defined by the Boltzmann tyranny. Tunnel field-effect transistors (TFETs) are considered promising low-power devices due to the band-to-band tunneling mechanism, which effectively avoids the thermionic limit. However, TFETs require the establishment of a staggered band alignment and currently lack effective techniques for adjusting the band offset. Here, by harnessing the robust ferroelectric field inherent to 2D CuInP₂S₆ (CIPS), a 2D WSe₂/MoS₂ heterojunction as well as a WSe₂ homojunction TFET controlled by ferroelectric gate are presented. The newly developed TFET achieves an ultra-low SS of 14.2 mV dec⁻¹ at room temperature, an on/off current ratio exceeding 10⁸, and a minimal hysteresis window below 10 mV. Additionally, the device demonstrates gate tunable negative differential resistance (NDR) characteristics with a very large peak-to-valley current ratio (PVCR) of 10.56 at room temperature. These findings underscore the significant promise of 2D ferroelectric tuning heterojunction and homojunction for future low-power electronic applications.