Tetsuya Iizuka;Ritaro Takenaka;Hao Xu;Asad A. Abidi
{"title":"Systematic Equation-Based Design of a 10-Bit, 500-MS/s Single-Channel SAR A/D Converter With 2-GHz Resolution Bandwidth","authors":"Tetsuya Iizuka;Ritaro Takenaka;Hao Xu;Asad A. Abidi","doi":"10.1109/OJSSCS.2024.3469109","DOIUrl":null,"url":null,"abstract":"A 10-b self-timed SAR A/D converter is designed in 28-nm FDSOI CMOS to convert at 500 MS/s. It maintains this effective number of bits across an input bandwidth of 2 GHz, because it will be used as one of eight identical converters in a time-interleaved system to reach a conversion rate of 4 GS/s. This circuit is based almost entirely on formal expressions for every building block circuit. This approach led to a strikingly short development time where every design choice was defensibly optimum and the prototype chip yielded near-textbook performance from the first silicon. The figure of merit is at the state of the art.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"147-162"},"PeriodicalIF":0.0000,"publicationDate":"2024-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10695771","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Open Journal of the Solid-State Circuits Society","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/10695771/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A 10-b self-timed SAR A/D converter is designed in 28-nm FDSOI CMOS to convert at 500 MS/s. It maintains this effective number of bits across an input bandwidth of 2 GHz, because it will be used as one of eight identical converters in a time-interleaved system to reach a conversion rate of 4 GS/s. This circuit is based almost entirely on formal expressions for every building block circuit. This approach led to a strikingly short development time where every design choice was defensibly optimum and the prototype chip yielded near-textbook performance from the first silicon. The figure of merit is at the state of the art.
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