Pub Date : 2026-01-15DOI: 10.1109/OJSSCS.2026.3652648
{"title":"IEEE Open Journal of the Solid-State Circuits Society","authors":"","doi":"10.1109/OJSSCS.2026.3652648","DOIUrl":"https://doi.org/10.1109/OJSSCS.2026.3652648","url":null,"abstract":"","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"6 ","pages":"C2-C2"},"PeriodicalIF":3.2,"publicationDate":"2026-01-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11355752","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145969436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-17DOI: 10.1109/OJSSCS.2025.3622592
Behzad Razavi
Millimeter-wave radios hold promise for supporting high data rates in wireless communication. A key challenge in the development of these radios relates to the generation of the local oscillator (LO) waveform(s) necessary for upconversion and downconversion. This article presents a number of such techniques in the context of four receivers operating at 28, 140, and 300 GHz. The proposed concepts focus on fundamental-mode LO synthesis and high-speed inductorless frequency dividers. New methods of LO phase shifting for beamforming applications are also introduced. The prototypes have been fabricated in 28-nm CMOS technology and exhibit rms jitter values ranging from 106 fs to 640 fs.
{"title":"LO Generation Techniques for Millimeter-Wave Receivers","authors":"Behzad Razavi","doi":"10.1109/OJSSCS.2025.3622592","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3622592","url":null,"abstract":"Millimeter-wave radios hold promise for supporting high data rates in wireless communication. A key challenge in the development of these radios relates to the generation of the local oscillator (LO) waveform(s) necessary for upconversion and downconversion. This article presents a number of such techniques in the context of four receivers operating at 28, 140, and 300 GHz. The proposed concepts focus on fundamental-mode LO synthesis and high-speed inductorless frequency dividers. New methods of LO phase shifting for beamforming applications are also introduced. The prototypes have been fabricated in 28-nm CMOS technology and exhibit rms jitter values ranging from 106 fs to 640 fs.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"310-321"},"PeriodicalIF":3.2,"publicationDate":"2025-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11206376","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145510084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-14DOI: 10.1109/OJSSCS.2025.3616271
Wei Deng;Minyoung Song;Aarno Pärssinen
{"title":"IEEE Open Journal of Solid-State Circuits Society Special Section on RF Circuits and Wireless Transceivers","authors":"Wei Deng;Minyoung Song;Aarno Pärssinen","doi":"10.1109/OJSSCS.2025.3616271","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3616271","url":null,"abstract":"","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"269-270"},"PeriodicalIF":3.2,"publicationDate":"2025-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11202698","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145352063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-16DOI: 10.1109/OJSSCS.2025.3610567
Archisman Ghosh;Md. Abdur Rahman;Debayan Das;Santosh Ghosh;Shreyas Sen
Mathematically secure cryptographic implementations leak critical information in terms of power, EM emanations, etc. Several circuit-level countermeasures are proposed to prevent leakage of the side channel at the source. Circuit-level countermeasures (e.g., IVR, STELLAR, WDDL, etc.) are often preferred as they are generic and have low overhead. They either dither the voltage randomly or attenuate the meaningful signature at the $V_{DD}$ port. Although any digital implementation has two generic ports, namely, clock and $V_{DD}$ , circuit-level countermeasures primarily focus on the $V_{DD}$ port, and countermeasures using the clock are mainly unexplored. System-level clock randomization is ineffective due to post-processing techniques. This work, for the first time, presents clock-based countermeasures by providing a controlled slew that exploits the inherent variability of digital circuits in terms of power consumption and transforms power/EM emanation into a complex function of data and slew, making it difficult for side-channel analysis. Due to this, minimum traces-to-disclosure (MTD) improves by $100times $ with respect to the unprotected one. Moreover, the slewed clock reduces the leaky frequency, and the clock randomization countermeasure is more effective as it becomes more difficult to post-process in the frequency domain. Clock slew and randomization together have a cumulative effect ($1800times $ ) more than the multiplication of individual techniques ($100times $ and $5times $ , respectively) at the cost of 11% area overhead, <3% power overhead (measured), and <6% performance overhead (measured).
{"title":"Exploiting Clock-Slew Dependent Variability in CMOS Digital Circuits Toward Power and EMSCA Resilience","authors":"Archisman Ghosh;Md. Abdur Rahman;Debayan Das;Santosh Ghosh;Shreyas Sen","doi":"10.1109/OJSSCS.2025.3610567","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3610567","url":null,"abstract":"Mathematically secure cryptographic implementations leak critical information in terms of power, EM emanations, etc. Several circuit-level countermeasures are proposed to prevent leakage of the side channel at the source. Circuit-level countermeasures (e.g., IVR, STELLAR, WDDL, etc.) are often preferred as they are generic and have low overhead. They either dither the voltage randomly or attenuate the meaningful signature at the <inline-formula> <tex-math>$V_{DD}$ </tex-math></inline-formula> port. Although any digital implementation has two generic ports, namely, clock and <inline-formula> <tex-math>$V_{DD}$ </tex-math></inline-formula>, circuit-level countermeasures primarily focus on the <inline-formula> <tex-math>$V_{DD}$ </tex-math></inline-formula> port, and countermeasures using the clock are mainly unexplored. System-level clock randomization is ineffective due to post-processing techniques. This work, for the first time, presents clock-based countermeasures by providing a controlled slew that exploits the inherent variability of digital circuits in terms of power consumption and transforms power/EM emanation into a complex function of data and slew, making it difficult for side-channel analysis. Due to this, minimum traces-to-disclosure (MTD) improves by <inline-formula> <tex-math>$100times $ </tex-math></inline-formula> with respect to the unprotected one. Moreover, the slewed clock reduces the leaky frequency, and the clock randomization countermeasure is more effective as it becomes more difficult to post-process in the frequency domain. Clock slew and randomization together have a cumulative effect (<inline-formula> <tex-math>$1800times $ </tex-math></inline-formula>) more than the multiplication of individual techniques (<inline-formula> <tex-math>$100times $ </tex-math></inline-formula> and <inline-formula> <tex-math>$5times $ </tex-math></inline-formula>, respectively) at the cost of 11% area overhead, <3% power overhead (measured), and <6% performance overhead (measured).","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"295-309"},"PeriodicalIF":3.2,"publicationDate":"2025-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11165158","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145405407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-16DOI: 10.1109/OJSSCS.2025.3610583
Jiawei Xu;Tianxiang Qu;Qinjing Pan;Yijie Li;Liheng Liu;Yuying Li;Jianhong Zhou;Chang Yao;Zhiliang Hong
Wearable platforms that concurrently acquire multiple physiological signals enable comprehensive health monitoring but impose stringent requirements on front-end circuit design. The reliable extraction of low-amplitude and low-frequency biosignals is hindered by electrode offset, noise, motion artifacts, and environmental interference. Recent efforts have advanced analog front ends (AFEs) for biopotential (ExG), bioimpedance (BioZ), and photoplethysmography (PPG) sensing, with emphasis on optimizing key metrics such as noise efficiency, input impedance, dynamic range, CMRR, and power consumption. In addition, digitally-assisted calibration and direct-digitization schemes have emerged as alternative design directions, offering enhanced robustness and scalability while introducing tradeoffs in complexity and energy efficiency. This review surveys these circuit techniques, analyzes their design tradeoffs, and outlines future opportunities for next-generation wearable biomedical interfaces.
{"title":"Analog Front-End Circuit Techniques for Wearable ExG, BioZ, and PPG Signal Acquisition: A Review","authors":"Jiawei Xu;Tianxiang Qu;Qinjing Pan;Yijie Li;Liheng Liu;Yuying Li;Jianhong Zhou;Chang Yao;Zhiliang Hong","doi":"10.1109/OJSSCS.2025.3610583","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3610583","url":null,"abstract":"Wearable platforms that concurrently acquire multiple physiological signals enable comprehensive health monitoring but impose stringent requirements on front-end circuit design. The reliable extraction of low-amplitude and low-frequency biosignals is hindered by electrode offset, noise, motion artifacts, and environmental interference. Recent efforts have advanced analog front ends (AFEs) for biopotential (ExG), bioimpedance (BioZ), and photoplethysmography (PPG) sensing, with emphasis on optimizing key metrics such as noise efficiency, input impedance, dynamic range, CMRR, and power consumption. In addition, digitally-assisted calibration and direct-digitization schemes have emerged as alternative design directions, offering enhanced robustness and scalability while introducing tradeoffs in complexity and energy efficiency. This review surveys these circuit techniques, analyzes their design tradeoffs, and outlines future opportunities for next-generation wearable biomedical interfaces.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"251-268"},"PeriodicalIF":3.2,"publicationDate":"2025-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11165115","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145255980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This work presents a fully unrolled on-chip deep reinforcement learning (DRL) module with a deep Q-network (DQN) and its system integration for integrated circuits control and functionality augmentation tasks, including voltage regulation of a cryogenic single-input triple-output dc–dc converter and recovery of RF fingerprints (RFFs) using a reconfigurable power amplifier (PA) under temperature variations. The complete DRL module features 6-bit fixed-point model parameters, 116 kB of memory, and 128 processing elements. It is equipped with on-chip training capabilities, fully unrolled on a 0.45-${mathrm { mm}}^{2}$ core area using 28-nm technology. The design achieves an efficiency of 0.12 nJ per action and a control latency of $4.925~mu $ s, with a maximum operational efficiency of 3.49 TOPS/W. Temperature effects on the chip are thoroughly demonstrated across a wide temperature range from 358 K ($85~^{circ }$ C) to 4.2 K (–$269~^{circ }$ C).
{"title":"A 0.45-mm² 3.49-TOPS/W Cryogenic Deep Reinforcement Learning Module for End-to-End Integrated Circuits Control","authors":"Jiachen Xu;John Kan;Yuyi Shen;Ethan Chen;Vanessa Chen","doi":"10.1109/OJSSCS.2025.3601153","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3601153","url":null,"abstract":"This work presents a fully unrolled on-chip deep reinforcement learning (DRL) module with a deep Q-network (DQN) and its system integration for integrated circuits control and functionality augmentation tasks, including voltage regulation of a cryogenic single-input triple-output dc–dc converter and recovery of RF fingerprints (RFFs) using a reconfigurable power amplifier (PA) under temperature variations. The complete DRL module features 6-bit fixed-point model parameters, 116 kB of memory, and 128 processing elements. It is equipped with on-chip training capabilities, fully unrolled on a 0.45-<inline-formula> <tex-math>${mathrm { mm}}^{2}$ </tex-math></inline-formula> core area using 28-nm technology. The design achieves an efficiency of 0.12 nJ per action and a control latency of <inline-formula> <tex-math>$4.925~mu $ </tex-math></inline-formula>s, with a maximum operational efficiency of 3.49 TOPS/W. Temperature effects on the chip are thoroughly demonstrated across a wide temperature range from 358 K (<inline-formula> <tex-math>$85~^{circ }$ </tex-math></inline-formula>C) to 4.2 K (–<inline-formula> <tex-math>$269~^{circ }$ </tex-math></inline-formula>C).","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"240-250"},"PeriodicalIF":3.2,"publicationDate":"2025-08-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11133470","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145027960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-11DOI: 10.1109/OJSSCS.2025.3597907
Sumit Pratap Singh;Mostafa Jafari Nokandi;Timo Rahkonen;Marko E. Leinonen;Aarno Pärssinen
This work presents a sliding-IF mixer-first IQ receiver front-end, in 130 nm SiGe BiCMOS technology with ${f_{t}}/{f_{mathrm { max}}}$ of 300 GHz/450 GHz, operating in 300 GHz band. For near-$f_{mathrm { max}}$ operation, the sliding-IF architecture eliminates the need for the local oscillator (LO) frequency to be the same as the carrier frequency. Consequently, the power consumption of the LO chain is significantly reduced with carefully optimized multiplier chain. Signal amplification is performed at the IF stage. LO frequency at two thirds and one third of the carrier frequency is generated, from an external 50 GHz LO signal using on-chip frequency doublers for RF and I/Q mixers, respectively. The receiver provides 15.2 dB of conversion gain, input-referred compression point of –17 dBm and single sideband noise figure of 29.5 dB at 310 GHz. The 3-dB RF and BB bandwidths are measured to be 26 GHz and 10 GHz, respectively. Despite operating at 0.69x$f_{mathrm { max}}$ , the receiver front-end operates with 16-quadrature amplitude modulation (QAM) modulation with 4 GHz, 64-QAM with 2 GHz and 256-QAM with 0.5 GHz wide modulated signal centered at low-baseband frequency with 8.2%, 5.5%, and 2.7% error vector magnitude (EVM), respectively. In low gain mode, the receiver offers a 10 dB improvement in the dynamic range with a 30% reduction in power consumption in the signal chain, which makes it one of the most energy efficient receiver front-ends in its class.
{"title":"A 300-GHz Band Sliding-IF I/Q Receiver Front-End in 130-nm SiGe Technology","authors":"Sumit Pratap Singh;Mostafa Jafari Nokandi;Timo Rahkonen;Marko E. Leinonen;Aarno Pärssinen","doi":"10.1109/OJSSCS.2025.3597907","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3597907","url":null,"abstract":"This work presents a sliding-IF mixer-first IQ receiver front-end, in 130 nm SiGe BiCMOS technology with <inline-formula> <tex-math>${f_{t}}/{f_{mathrm { max}}}$ </tex-math></inline-formula> of 300 GHz/450 GHz, operating in 300 GHz band. For near-<inline-formula> <tex-math>$f_{mathrm { max}}$ </tex-math></inline-formula> operation, the sliding-IF architecture eliminates the need for the local oscillator (LO) frequency to be the same as the carrier frequency. Consequently, the power consumption of the LO chain is significantly reduced with carefully optimized multiplier chain. Signal amplification is performed at the IF stage. LO frequency at two thirds and one third of the carrier frequency is generated, from an external 50 GHz LO signal using on-chip frequency doublers for RF and I/Q mixers, respectively. The receiver provides 15.2 dB of conversion gain, input-referred compression point of –17 dBm and single sideband noise figure of 29.5 dB at 310 GHz. The 3-dB RF and BB bandwidths are measured to be 26 GHz and 10 GHz, respectively. Despite operating at 0.69x<inline-formula> <tex-math>$f_{mathrm { max}}$ </tex-math></inline-formula>, the receiver front-end operates with 16-quadrature amplitude modulation (QAM) modulation with 4 GHz, 64-QAM with 2 GHz and 256-QAM with 0.5 GHz wide modulated signal centered at low-baseband frequency with 8.2%, 5.5%, and 2.7% error vector magnitude (EVM), respectively. In low gain mode, the receiver offers a 10 dB improvement in the dynamic range with a 30% reduction in power consumption in the signal chain, which makes it one of the most energy efficient receiver front-ends in its class.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"284-294"},"PeriodicalIF":3.2,"publicationDate":"2025-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11122561","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145351979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-11DOI: 10.1109/OJSSCS.2025.3597909
Nicolás Wainstein;Eran Avitay;Eugene Avner
This article presents a digital delay-locked loop (DLL) with binary search (BS) locking, designed to cover a broad frequency-range from 533 MHz to 4.26 GHz. The BS locking scheme optimizes the locking time, reducing it from a linear to a logarithmic function, completing in B+1 cycles, where B represents the digital-to-analog converter (DAC) resolution controlling the voltage-controlled delay line (VCDL). At the start of the BS process, large step sizes can cause significant bias overshoots, potentially leading to clock failure conditions (i.e., clocks fail to propagate through the VCDL). To address this issue, a toggle detector is introduced to monitor clock activity and adjust the BS controller. Upon detecting a stalled clock, the controller reverts the DAC code to the previous working code and resumes the BS with a reduced step size. Fabricated in a 3-nm FinFET CMOS process, the proposed DLL achieves a locking time of under 10.5 ns while consuming 5.4 mW from a 0.75-V supply at 4.26 GHz. The measured performance includes a high resolution of 0.73 ps, with a static phase error of 0.73 ps, RMS jitter of 1.2 ps, and peak-to-peak jitter of 4.9 ps. The proposed design achieves state-of-the-art power figure of merit (FoM) of 0.82 pJ and DLL locking and resolution FoM of 0.01 pJ$cdot $ ns2.
{"title":"Fast-Locking and High-Resolution DLL With Binary Search and Clock Failure Detection for Wide Frequency Ranges in 3-nm FinFET CMOS","authors":"Nicolás Wainstein;Eran Avitay;Eugene Avner","doi":"10.1109/OJSSCS.2025.3597909","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3597909","url":null,"abstract":"This article presents a digital delay-locked loop (DLL) with binary search (BS) locking, designed to cover a broad frequency-range from 533 MHz to 4.26 GHz. The BS locking scheme optimizes the locking time, reducing it from a linear to a logarithmic function, completing in B+1 cycles, where B represents the digital-to-analog converter (DAC) resolution controlling the voltage-controlled delay line (VCDL). At the start of the BS process, large step sizes can cause significant bias overshoots, potentially leading to clock failure conditions (i.e., clocks fail to propagate through the VCDL). To address this issue, a toggle detector is introduced to monitor clock activity and adjust the BS controller. Upon detecting a stalled clock, the controller reverts the DAC code to the previous working code and resumes the BS with a reduced step size. Fabricated in a 3-nm FinFET CMOS process, the proposed DLL achieves a locking time of under 10.5 ns while consuming 5.4 mW from a 0.75-V supply at 4.26 GHz. The measured performance includes a high resolution of 0.73 ps, with a static phase error of 0.73 ps, RMS jitter of 1.2 ps, and peak-to-peak jitter of 4.9 ps. The proposed design achieves state-of-the-art power figure of merit (FoM) of 0.82 pJ and DLL locking and resolution FoM of 0.01 pJ<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>ns2.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"229-239"},"PeriodicalIF":3.2,"publicationDate":"2025-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11122556","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145011322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-04DOI: 10.1109/OJSSCS.2025.3595832
Wen Chen;Yiyang Shu;Xun Luo
In this article, a wideband millimeter-wave (mm-wave) fractional-N subsampling phase-locked loop (SSPLL) with low jitter and low power consumption is proposed. A dividerless unequal-REF-delay frequency-tracking loop (URD-FTL) is introduced to ensure frequency locking over a wide mm-wave frequency range. By running the URD-FTL at the reference frequency instead of the oscillation frequency, the proposed design eliminates the need for high-power mm-wave frequency dividers. The URD-FTL is disabled while phase locking without sacrificing the jitter performance. Besides, the mm-wave quad-mode oscillator and digital-to-time converter are integrated in the SSPLL to achieve a wideband fractional operation. The proposed fractional-N SSPLL is fabricated in a 40-nm CMOS technology and occupies a core area of 0.17 mm2. Measurements exhibit an output frequency range of 62.5% from 21.8 to 41.6 GHz with a 100-MHz reference. The total power consumption is 11.6–14.8 mW, while the URD-FTL consumes only $680~mu $ W. The SSPLL achieves a 135.4–167.5-fs jitter within the output frequency range, which leads to an FoM$rm _{textbf {j}}$ from −246.7 to −243.9 dB. Meanwhile, the proposed SSPLL features a frequency locking acquisition.
{"title":"A 21.8–41.6-GHz Fractional-N Subsampling PLL With Dividerless Unequal-REF-Delay Frequency Tracking","authors":"Wen Chen;Yiyang Shu;Xun Luo","doi":"10.1109/OJSSCS.2025.3595832","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3595832","url":null,"abstract":"In this article, a wideband millimeter-wave (mm-wave) fractional-N subsampling phase-locked loop (SSPLL) with low jitter and low power consumption is proposed. A dividerless unequal-REF-delay frequency-tracking loop (URD-FTL) is introduced to ensure frequency locking over a wide mm-wave frequency range. By running the URD-FTL at the reference frequency instead of the oscillation frequency, the proposed design eliminates the need for high-power mm-wave frequency dividers. The URD-FTL is disabled while phase locking without sacrificing the jitter performance. Besides, the mm-wave quad-mode oscillator and digital-to-time converter are integrated in the SSPLL to achieve a wideband fractional operation. The proposed fractional-N SSPLL is fabricated in a 40-nm CMOS technology and occupies a core area of 0.17 mm2. Measurements exhibit an output frequency range of 62.5% from 21.8 to 41.6 GHz with a 100-MHz reference. The total power consumption is 11.6–14.8 mW, while the URD-FTL consumes only <inline-formula> <tex-math>$680~mu $ </tex-math></inline-formula>W. The SSPLL achieves a 135.4–167.5-fs jitter within the output frequency range, which leads to an FoM<inline-formula> <tex-math>$rm _{textbf {j}}$ </tex-math></inline-formula> from −246.7 to −243.9 dB. Meanwhile, the proposed SSPLL features a frequency locking acquisition.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"271-283"},"PeriodicalIF":3.2,"publicationDate":"2025-08-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11112717","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145351976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-18DOI: 10.1109/OJSSCS.2025.3561812
Youngcheol Chae;Mike Shuo-Wei Chen
{"title":"IEEE Open Journal of the Solid-State Circuits Society Special Section on Data Converters","authors":"Youngcheol Chae;Mike Shuo-Wei Chen","doi":"10.1109/OJSSCS.2025.3561812","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3561812","url":null,"abstract":"","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"144-144"},"PeriodicalIF":0.0,"publicationDate":"2025-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11039224","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144314856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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