Pub Date : 2026-02-24DOI: 10.1109/OJSSCS.2026.3667840
Chun-Yu Lin;Ming-Dou Ker
Electrostatic discharge (ESD) remains a critical reliability issue in CMOS technologies. This article reviews the fundamentals of ESD phenomena and introduces representative on-chip protection structures. To address the shrinking margin between supply voltage and gate oxide breakdown, the concept of the ESD design window is introduced as a fundamental constraint for selecting and sizing protection devices. The inherent tradeoff between ESD robustness and latch-up immunity is also addressed, highlighting strategies to prevent accidental activation during normal operation. It is further indicated that effective ESD protection is a comprehensive chip-level requirement that extends beyond I/O pads to include robust power-rail clamping and internal protection. Diode-based protection, silicon-controlled rectifier (SCR)-based devices, and MOS clamps are discussed with emphasis on their operating principles, discharge paths, and design tradeoffs. The coordination between I/O protection and power-rail clamps is highlighted as an essential requirement for forming complete discharge paths during ESD events. In addition to presenting the key device and circuit concepts, this article also clarifies how these structures are typically integrated into practical chip designs, providing readers with both intuitive understanding and circuit-level design guidelines that can be directly applied in design practice. Finally, future challenges are outlined, including the impact of advanced technology scaling, 3-D integration, chiplet-based architectures, and increasingly stringent system-level standards. By combining fundamental insights with circuit-level perspectives, this article aims to serve as a clear and accessible tutorial foundation, helping circuit designers and researchers build a comprehensive understanding of ESD protection for modern and future semiconductor technologies, and supporting continued progress in reliable electronic system design.
{"title":"ESD Protection Design: Fundamentals and Advanced Strategies","authors":"Chun-Yu Lin;Ming-Dou Ker","doi":"10.1109/OJSSCS.2026.3667840","DOIUrl":"https://doi.org/10.1109/OJSSCS.2026.3667840","url":null,"abstract":"Electrostatic discharge (ESD) remains a critical reliability issue in CMOS technologies. This article reviews the fundamentals of ESD phenomena and introduces representative on-chip protection structures. To address the shrinking margin between supply voltage and gate oxide breakdown, the concept of the ESD design window is introduced as a fundamental constraint for selecting and sizing protection devices. The inherent tradeoff between ESD robustness and latch-up immunity is also addressed, highlighting strategies to prevent accidental activation during normal operation. It is further indicated that effective ESD protection is a comprehensive chip-level requirement that extends beyond I/O pads to include robust power-rail clamping and internal protection. Diode-based protection, silicon-controlled rectifier (SCR)-based devices, and MOS clamps are discussed with emphasis on their operating principles, discharge paths, and design tradeoffs. The coordination between I/O protection and power-rail clamps is highlighted as an essential requirement for forming complete discharge paths during ESD events. In addition to presenting the key device and circuit concepts, this article also clarifies how these structures are typically integrated into practical chip designs, providing readers with both intuitive understanding and circuit-level design guidelines that can be directly applied in design practice. Finally, future challenges are outlined, including the impact of advanced technology scaling, 3-D integration, chiplet-based architectures, and increasingly stringent system-level standards. By combining fundamental insights with circuit-level perspectives, this article aims to serve as a clear and accessible tutorial foundation, helping circuit designers and researchers build a comprehensive understanding of ESD protection for modern and future semiconductor technologies, and supporting continued progress in reliable electronic system design.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"6 ","pages":"61-76"},"PeriodicalIF":3.2,"publicationDate":"2026-02-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11408826","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147440691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ultrafast time-compressive CMOS image sensors based on multitap charge modulators can capture light-in flight using coded exposure masks on the focal plane. Transient images can then be reconstructed using iterative methods or deep learning models. Although the image sensor is based on indirect time-of-flight (ToF) image sensors, the reconstructed images are equivalent to those captured by direct ToF (D-ToF) image sensors. Important design parameters of the image sensor include the pixel block size and the number of taps of the charge modulator. Several constraints regarding the charge transfer of the multitap charge modulator, the hamming distance between exposure codes at adjacent timings, and the minimal time window duration must be considered when designing exposure codes. The influence of these factors on the fidelity of the reconstructed images is analyzed numerically. The results show that a pixel block size of $4times 4$ is optimal and that four or more taps are required for light detection and ranging (LiDAR) applications when 32 transient images of light-in flight are reconstructed. To demonstrate LiDAR in a scene with multipath interference, two objects were observed through a weakly diffusive sheet. The temporal resolution, as defined by the clock period of the exposure codes, was 1.65 ns. Multiple reflections were reconstructed using an iterative method (TVAL3) and a deep learning model (ADMM-Net). Although the waveforms of optical pulses reconstructed by TVAL3 are distorted, the amplitudes are more accurate. Conversely, although ADMM-Net reconstructs sharper optical pulses, the amplitudes are inaccurate. To achieve the shorter temporal resolution required for time-resolved diffuse optical tomography (DOT) and fluorescence lifetime imaging (FLIm), the feasibility of heterodyne compression was demonstrated through simulation.
{"title":"Ultrafast Time-Compressive CMOS Image Sensors Based on Multitap Charge Modulators for Filming Light-In Flight","authors":"Keiichiro Kagawa;Daisuke Hayashi;Arashi Takakura;Yuto Umeki;Michitaka Yoshida;Keita Yasutomi;Shoji Kawahito;Youngcheol Chae;Hajime Nagahara","doi":"10.1109/OJSSCS.2026.3660622","DOIUrl":"https://doi.org/10.1109/OJSSCS.2026.3660622","url":null,"abstract":"Ultrafast time-compressive CMOS image sensors based on multitap charge modulators can capture light-in flight using coded exposure masks on the focal plane. Transient images can then be reconstructed using iterative methods or deep learning models. Although the image sensor is based on indirect time-of-flight (ToF) image sensors, the reconstructed images are equivalent to those captured by direct ToF (D-ToF) image sensors. Important design parameters of the image sensor include the pixel block size and the number of taps of the charge modulator. Several constraints regarding the charge transfer of the multitap charge modulator, the hamming distance between exposure codes at adjacent timings, and the minimal time window duration must be considered when designing exposure codes. The influence of these factors on the fidelity of the reconstructed images is analyzed numerically. The results show that a pixel block size of <inline-formula> <tex-math>$4times 4$ </tex-math></inline-formula> is optimal and that four or more taps are required for light detection and ranging (LiDAR) applications when 32 transient images of light-in flight are reconstructed. To demonstrate LiDAR in a scene with multipath interference, two objects were observed through a weakly diffusive sheet. The temporal resolution, as defined by the clock period of the exposure codes, was 1.65 ns. Multiple reflections were reconstructed using an iterative method (TVAL3) and a deep learning model (ADMM-Net). Although the waveforms of optical pulses reconstructed by TVAL3 are distorted, the amplitudes are more accurate. Conversely, although ADMM-Net reconstructs sharper optical pulses, the amplitudes are inaccurate. To achieve the shorter temporal resolution required for time-resolved diffuse optical tomography (DOT) and fluorescence lifetime imaging (FLIm), the feasibility of heterodyne compression was demonstrated through simulation.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"6 ","pages":"47-60"},"PeriodicalIF":3.2,"publicationDate":"2026-02-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11370880","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147362554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-02-03DOI: 10.1109/OJSSCS.2026.3660196
Sudipto Chakraborty;Marcel Kossel;Matthias Brändli;Pier-Andrea Francese;Mridula Prathapan;Pat Rosno;Mark Yeck;John F. Bulzacchelli;Daniil Frolov;David J. Frank;Ray Richetta;Timothy J. Schmerbeck;Daniel Ramirez;Christian W. Baks;Ken Inoue;Cezar Zota;Austin Carter;Bryce Snell;Devin Underwood;Kevin Tien;Bodhisatwa Sadhu;Daniel J. Friedman
This article presents design approaches for two radio frequency (RF) arbitrary waveform generators (AWGs) operating at cryogenic temperatures using FinFET CMOS technologies. This article presents power, performance, and area tradeoffs for highly scaled quantum computing systems using different types of qubits (spin and transmons). The first considered design uses a direct digital synthesis (DDS) approach to provide a wide bandwidth (1-18 GHz) control solution for spin qubits. As this design point was implemented in two technology nodes (14- and 7-nm CMOS), it offers a window into the benefits for this application arising from technology scaling. Furthermore, the DDS architecture offers flexibility to meet the requirements of the rapidly evolving requirements of spin qubits and naturally supports a high degree of programmability of the amplitude, phase, duration, frequency, and spacing of control waveforms. The DDS-based wideband RF digital-to-analog converter (DAC) was demonstrated to be operational over the full 1–18-GHz target operating range, providing sufficient bandwidth for control signals for state-of-the-art spin-qubit platforms. The second design approach uses various techniques for highly reconfigurable, low-power control waveform generation for transmon qubits using current-mode analog design. This second approach, implemented using two 14-nm FinFET CMOS designs, has enabled the investigation of design-driven power scaling techniques. The DDS-based single spin-qubit controller consumes 40-140 mW, occupying 0.5 mm2 in a 14-nm FinFET node implementation, and 30-68 mW, occupying 0.1 mm2 in a 7-nm FinFET node. The current-mode transmon qubit controller designs, both implemented in 14-nm FinFET, consume 23 and 12.8 mW, respectively, occupying 1.61 and 1.32 mm2 per qubit controller, respectively.
{"title":"Cryogenic CMOS RF AWGs for Qubit Control","authors":"Sudipto Chakraborty;Marcel Kossel;Matthias Brändli;Pier-Andrea Francese;Mridula Prathapan;Pat Rosno;Mark Yeck;John F. Bulzacchelli;Daniil Frolov;David J. Frank;Ray Richetta;Timothy J. Schmerbeck;Daniel Ramirez;Christian W. Baks;Ken Inoue;Cezar Zota;Austin Carter;Bryce Snell;Devin Underwood;Kevin Tien;Bodhisatwa Sadhu;Daniel J. Friedman","doi":"10.1109/OJSSCS.2026.3660196","DOIUrl":"https://doi.org/10.1109/OJSSCS.2026.3660196","url":null,"abstract":"This article presents design approaches for two radio frequency (RF) arbitrary waveform generators (AWGs) operating at cryogenic temperatures using FinFET CMOS technologies. This article presents power, performance, and area tradeoffs for highly scaled quantum computing systems using different types of qubits (spin and transmons). The first considered design uses a direct digital synthesis (DDS) approach to provide a wide bandwidth (1-18 GHz) control solution for spin qubits. As this design point was implemented in two technology nodes (14- and 7-nm CMOS), it offers a window into the benefits for this application arising from technology scaling. Furthermore, the DDS architecture offers flexibility to meet the requirements of the rapidly evolving requirements of spin qubits and naturally supports a high degree of programmability of the amplitude, phase, duration, frequency, and spacing of control waveforms. The DDS-based wideband RF digital-to-analog converter (DAC) was demonstrated to be operational over the full 1–18-GHz target operating range, providing sufficient bandwidth for control signals for state-of-the-art spin-qubit platforms. The second design approach uses various techniques for highly reconfigurable, low-power control waveform generation for transmon qubits using current-mode analog design. This second approach, implemented using two 14-nm FinFET CMOS designs, has enabled the investigation of design-driven power scaling techniques. The DDS-based single spin-qubit controller consumes 40-140 mW, occupying 0.5 mm<sup>2</sup> in a 14-nm FinFET node implementation, and 30-68 mW, occupying 0.1 mm<sup>2</sup> in a 7-nm FinFET node. The current-mode transmon qubit controller designs, both implemented in 14-nm FinFET, consume 23 and 12.8 mW, respectively, occupying 1.61 and 1.32 mm<sup>2</sup> per qubit controller, respectively.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"6 ","pages":"77-92"},"PeriodicalIF":3.2,"publicationDate":"2026-02-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11370158","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147440495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-26DOI: 10.1109/OJSSCS.2026.3652568
Woogeun Rhee
{"title":"New Associate Editors","authors":"Woogeun Rhee","doi":"10.1109/OJSSCS.2026.3652568","DOIUrl":"https://doi.org/10.1109/OJSSCS.2026.3652568","url":null,"abstract":"","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"6 ","pages":"1-2"},"PeriodicalIF":3.2,"publicationDate":"2026-01-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11363466","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146082132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-26DOI: 10.1109/OJSSCS.2026.3658141
{"title":"2025 Index IEEE Open Journal of the Solid-State Circuits Society Vol. 5","authors":"","doi":"10.1109/OJSSCS.2026.3658141","DOIUrl":"https://doi.org/10.1109/OJSSCS.2026.3658141","url":null,"abstract":"","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"524-537"},"PeriodicalIF":3.2,"publicationDate":"2026-01-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11364040","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146082098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-21DOI: 10.1109/OJSSCS.2025.3643485
Po-Chiun Huang;Pieter Harpe
{"title":"Special Section on Temperature Resilient Systems and Circuits","authors":"Po-Chiun Huang;Pieter Harpe","doi":"10.1109/OJSSCS.2025.3643485","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3643485","url":null,"abstract":"","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"454-455"},"PeriodicalIF":3.2,"publicationDate":"2026-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11360104","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146026551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-21DOI: 10.1109/OJSSCS.2025.3648687
Inhee Lee;Phillip Nadeau
{"title":"Special Section on Energy-Efficient Biomedical Systems and Circuits","authors":"Inhee Lee;Phillip Nadeau","doi":"10.1109/OJSSCS.2025.3648687","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3648687","url":null,"abstract":"","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"322-323"},"PeriodicalIF":3.2,"publicationDate":"2026-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11360106","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146026496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-21DOI: 10.1109/OJSSCS.2025.3640567
Shenggao Li;Tony Chan Carusone
{"title":"Special Section on Chiplet Interconnects and Architectures","authors":"Shenggao Li;Tony Chan Carusone","doi":"10.1109/OJSSCS.2025.3640567","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3640567","url":null,"abstract":"","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"400-400"},"PeriodicalIF":3.2,"publicationDate":"2026-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11360105","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146026632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-19DOI: 10.1109/OJSSCS.2026.3655336
Minseob Shim;Donghyun Kim;Jong-Hun Kim;Mingyu Kim;Yuyang Li;Ehab A. Hamed;Xiao Wu;Yimai Peng;Junwon Jeong;Wanyeong Jung;Yoonmyung Lee;Se-Un Shin;Yun-Jae Won;Inhee Lee
This article provides a comprehensive review of power management circuit techniques for millimeter-scale biomedical sensing systems, which operate under strict power and energy constraints. It begins by introducing a miniature sensing platform and outlining the key challenges associated with limited energy availability in such ultrasmall devices. The discussion then highlights advances in circuit design for efficient power conversion, battery management, ambient energy harvesting, and wireless power transfer. By examining these techniques, this article aims to clarify the major design challenges and emerging solutions that are driving the development of next-generation miniature biomedical electronics.
{"title":"Power Management Circuit Techniques for Miniature Biomedical Sensing Systems","authors":"Minseob Shim;Donghyun Kim;Jong-Hun Kim;Mingyu Kim;Yuyang Li;Ehab A. Hamed;Xiao Wu;Yimai Peng;Junwon Jeong;Wanyeong Jung;Yoonmyung Lee;Se-Un Shin;Yun-Jae Won;Inhee Lee","doi":"10.1109/OJSSCS.2026.3655336","DOIUrl":"https://doi.org/10.1109/OJSSCS.2026.3655336","url":null,"abstract":"This article provides a comprehensive review of power management circuit techniques for millimeter-scale biomedical sensing systems, which operate under strict power and energy constraints. It begins by introducing a miniature sensing platform and outlining the key challenges associated with limited energy availability in such ultrasmall devices. The discussion then highlights advances in circuit design for efficient power conversion, battery management, ambient energy harvesting, and wireless power transfer. By examining these techniques, this article aims to clarify the major design challenges and emerging solutions that are driving the development of next-generation miniature biomedical electronics.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"6 ","pages":"25-46"},"PeriodicalIF":3.2,"publicationDate":"2026-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11357517","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146175847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-15DOI: 10.1109/OJSSCS.2026.3652648
{"title":"IEEE Open Journal of the Solid-State Circuits Society","authors":"","doi":"10.1109/OJSSCS.2026.3652648","DOIUrl":"https://doi.org/10.1109/OJSSCS.2026.3652648","url":null,"abstract":"","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"6 ","pages":"C2-C2"},"PeriodicalIF":3.2,"publicationDate":"2026-01-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11355752","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145969436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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