Pub Date : 2025-02-25DOI: 10.1109/OJSSCS.2025.3545275
{"title":"2024 Index IEEE Open Journal of the Solid-State Circuits Society Vol. 4","authors":"","doi":"10.1109/OJSSCS.2025.3545275","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3545275","url":null,"abstract":"","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"381-390"},"PeriodicalIF":0.0,"publicationDate":"2025-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10903144","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143489170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-20DOI: 10.1109/OJSSCS.2025.3526922
Woogeun Rhee
{"title":"Editorial Message From the Incoming Editor-in-Chief","authors":"Woogeun Rhee","doi":"10.1109/OJSSCS.2025.3526922","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3526922","url":null,"abstract":"","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"378-378"},"PeriodicalIF":0.0,"publicationDate":"2025-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10896768","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143455288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-19DOI: 10.1109/OJSSCS.2025.3526924
Sam Palermo;Jaeduk Han
{"title":"Editorial Special section on High-Performance Wireline Transceiver Circuits","authors":"Sam Palermo;Jaeduk Han","doi":"10.1109/OJSSCS.2025.3526924","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3526924","url":null,"abstract":"","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"379-380"},"PeriodicalIF":0.0,"publicationDate":"2025-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10892322","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143446202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-07DOI: 10.1109/OJSSCS.2025.3526923
Salvatore Levantino;Wanghua Wu
{"title":"Editorial Special Section on High-Performance Frequency Synthesizers","authors":"Salvatore Levantino;Wanghua Wu","doi":"10.1109/OJSSCS.2025.3526923","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3526923","url":null,"abstract":"","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"376-377"},"PeriodicalIF":0.0,"publicationDate":"2025-02-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10877780","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143360883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A modular 4.26 Mb SRAM based on a 82 Kb/block structure with mixed signal logic is fabricated, characterized, and demonstrated with full functionality in a 3-nm nanosheet (NS) technology. Designed macros utilize new circuits for supply boosting, read, and write assist techniques. The proposed circuits are evaluated extensively and compared to prior techniques. Statistical simulations are used to predict the benefits of these circuits in the context of dual supply use. Through programmable local clock and wordline (WL) pulsewidths, SRAM cell margins and speeds are demonstrated through hardware measurement. Stability assists as well as dual supply techniques are used to demonstrate how noise can be suppressed during traditional memory operations (single WL on), as well as to support mixed-signal logic block operation (multiple WLs on). Functionality is shown down to a cell supply of 0.45 V with an estimated margin/speed of 6 GHz for SRAM cells (high density—$0.026~mu $ m2, and high current—$0.032~mu $ m2).
{"title":"SRAM and Mixed-Signal Logic With Noise Immunity in 3-nm Nano-Sheet Technology","authors":"Rajiv V. Joshi;J. Frougier;Alberto Cestero;Crystal Castellanos;Sudipto Chakraborty;Carl Radens;M. Silvestre;S. Lucarini;I. Ahsan;E. Leobandung","doi":"10.1109/OJSSCS.2024.3524495","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3524495","url":null,"abstract":"A modular 4.26 Mb SRAM based on a 82 Kb/block structure with mixed signal logic is fabricated, characterized, and demonstrated with full functionality in a 3-nm nanosheet (NS) technology. Designed macros utilize new circuits for supply boosting, read, and write assist techniques. The proposed circuits are evaluated extensively and compared to prior techniques. Statistical simulations are used to predict the benefits of these circuits in the context of dual supply use. Through programmable local clock and wordline (WL) pulsewidths, SRAM cell margins and speeds are demonstrated through hardware measurement. Stability assists as well as dual supply techniques are used to demonstrate how noise can be suppressed during traditional memory operations (single WL on), as well as to support mixed-signal logic block operation (multiple WLs on). Functionality is shown down to a cell supply of 0.45 V with an estimated margin/speed of 6 GHz for SRAM cells (high density—<inline-formula> <tex-math>$0.026~mu $ </tex-math></inline-formula>m<sup>2</sup>, and high current—<inline-formula> <tex-math>$0.032~mu $ </tex-math></inline-formula>m<sup>2</sup>).","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"60-74"},"PeriodicalIF":0.0,"publicationDate":"2025-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10839490","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143388591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-06DOI: 10.1109/OJSSCS.2025.3526132
Chongyun Zhang;Fuzhan Chen;Li Wang;Lin Wang;C. Patrick Yue
The ever-increasing demand for data centers and high-performance computing systems necessitate power-efficient, low-latency, and high-density interconnect design. This article reviews and analyzes recent design challenges and advances of optical transceiver, phase-locked loop (PLL), and clock and data recovery (CDR) for data center applications with a distance of ~100 m. At the transmitter side, nonidealities of the widely used vertical-cavity surface-emitting laser (VCSEL) are described, followed by reviews on existing compensation techniques for those nonidealities. At the receiver side, tradeoffs between gain, bandwidth (BW), noise, and linearity in PAM-4 optical receiver design are introduced, and design methods to improve the power efficiency and BW density are particularly discussed. Regarding clock generation which directly affects the performance of the transceiver, compact PLL design techniques focusing on in-band phase noise reduction and low-jitter performance are described. The signal integrity of PAM-4 signal becomes more susceptible to noise and jitter due to reduced signal level spacing. To address the uncorrelated jitter accumulation within the CDR which limits the signal quality and transmission distance, jitter compensation schemes in CDR design are described. And the clock distribution techniques for multilane transceiver systems are discussed.
{"title":"Recent Advances of High-Speed Short-Reach Optical Interconnects for Data Centers","authors":"Chongyun Zhang;Fuzhan Chen;Li Wang;Lin Wang;C. Patrick Yue","doi":"10.1109/OJSSCS.2025.3526132","DOIUrl":"https://doi.org/10.1109/OJSSCS.2025.3526132","url":null,"abstract":"The ever-increasing demand for data centers and high-performance computing systems necessitate power-efficient, low-latency, and high-density interconnect design. This article reviews and analyzes recent design challenges and advances of optical transceiver, phase-locked loop (PLL), and clock and data recovery (CDR) for data center applications with a distance of ~100 m. At the transmitter side, nonidealities of the widely used vertical-cavity surface-emitting laser (VCSEL) are described, followed by reviews on existing compensation techniques for those nonidealities. At the receiver side, tradeoffs between gain, bandwidth (BW), noise, and linearity in PAM-4 optical receiver design are introduced, and design methods to improve the power efficiency and BW density are particularly discussed. Regarding clock generation which directly affects the performance of the transceiver, compact PLL design techniques focusing on in-band phase noise reduction and low-jitter performance are described. The signal integrity of PAM-4 signal becomes more susceptible to noise and jitter due to reduced signal level spacing. To address the uncorrelated jitter accumulation within the CDR which limits the signal quality and transmission distance, jitter compensation schemes in CDR design are described. And the clock distribution techniques for multilane transceiver systems are discussed.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"86-100"},"PeriodicalIF":0.0,"publicationDate":"2025-01-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10824885","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143455318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-31DOI: 10.1109/OJSSCS.2024.3524493
Asad A. Abidi;David Murphy
CMOS oscillators that produce high frequencies with good spectral purity or low jitter are almost always realized as differential LC oscillators. This article gives a comprehensive treatment of this circuit for the practitioner who must make design choices and tradeoffs, and for the newcomer who wants to learn to do so. Phase noise is presented in the form of transfer functions from various noise sources, leading to compact, accurate expressions that guide design. Best practices for IC layout and operation at low voltages are given.
{"title":"How to Design a Differential CMOS LC Oscillator","authors":"Asad A. Abidi;David Murphy","doi":"10.1109/OJSSCS.2024.3524493","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3524493","url":null,"abstract":"CMOS oscillators that produce high frequencies with good spectral purity or low jitter are almost always realized as differential LC oscillators. This article gives a comprehensive treatment of this circuit for the practitioner who must make design choices and tradeoffs, and for the newcomer who wants to learn to do so. Phase noise is presented in the form of transfer functions from various noise sources, leading to compact, accurate expressions that guide design. Best practices for IC layout and operation at low voltages are given.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"45-59"},"PeriodicalIF":0.0,"publicationDate":"2024-12-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10818782","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143388590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-26DOI: 10.1109/OJSSCS.2024.3523245
Sumukh Prashant Bhanushali;Arindam Sanyal
This work presents an OTA-free pipelined passive noise-shaping successive approximation register (NS-SAR) + VCO ADC that offers high resolution (>12-bit) with only a 5-bit NS-SAR stage and $4times $ –$36times $ lower sampling capacitor compared to state-of-the-art NS-SARs with similar ENOB. Pipelining the NS-SAR and VCO stage linearizes VCO by reducing its input swing, increases the VCO integration time and its energy efficiency, and improves the SFDR of ADC by suppressing frequency dependency of interstage gain. We demonstrate a simple calibration technique to extract interstage gain and track VCO gain accurately in the background. Fabricated in 65-nm CMOS, the prototype ADC achieves the best Walden FoM among state-of-the-art passive NS-SAR ADCs in similar technology and consumes 0.12 mW with SNDR/SFDR of 74.3/89.1 dB at 13.2 fJ/step for OSR of 9.
{"title":"A 13.2-fJ/Step 74.3-dB SNDR Pipelined Noise-Shaping SAR+VCO ADC","authors":"Sumukh Prashant Bhanushali;Arindam Sanyal","doi":"10.1109/OJSSCS.2024.3523245","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3523245","url":null,"abstract":"This work presents an OTA-free pipelined passive noise-shaping successive approximation register (NS-SAR) + VCO ADC that offers high resolution (>12-bit) with only a 5-bit NS-SAR stage and <inline-formula> <tex-math>$4times $ </tex-math></inline-formula>–<inline-formula> <tex-math>$36times $ </tex-math></inline-formula> lower sampling capacitor compared to state-of-the-art NS-SARs with similar ENOB. Pipelining the NS-SAR and VCO stage linearizes VCO by reducing its input swing, increases the VCO integration time and its energy efficiency, and improves the SFDR of ADC by suppressing frequency dependency of interstage gain. We demonstrate a simple calibration technique to extract interstage gain and track VCO gain accurately in the background. Fabricated in 65-nm CMOS, the prototype ADC achieves the best Walden FoM among state-of-the-art passive NS-SAR ADCs in similar technology and consumes 0.12 mW with SNDR/SFDR of 74.3/89.1 dB at 13.2 fJ/step for OSR of 9.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"75-85"},"PeriodicalIF":0.0,"publicationDate":"2024-12-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10816503","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143422856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-19DOI: 10.1109/OJSSCS.2024.3520525
Lucas Moura Santana;Ewout Martens;Jorge Lagos;Piet Wambacq;Jan Craninckx
This work presents a $2times $ time-interleaved (TI) delta-sigma modulator (DSM) analog-to-digital converter (ADC) leveraging a 6-b noise-coupled (NC) noise-shaping (NS) SAR quantizer. A novel technique to implement the noise coupling mid-quantization is presented to relax the timing bottleneck by parallelizing the operations needed for coupling. The loop filter is implemented using power-efficient, no hold-phase ring amplifiers, with an input capacitor reset presampling to reduce kickback noise in the input network. The complete ADC clocks at a sampling rate of 1.4 GS/s, which is one of the highest among all discrete-time (DT) DSM ADCs and TI NS ADCs to date, and achieves 67/72-dB SNDR/SNR over a 70-MHz bandwidth while consuming 32 mW.
{"title":"A 70-MHz Bandwidth Time-Interleaved Noise-Shaping SAR-Assisted Delta-Sigma ADC With Digital Cross-Coupling in 28-nm CMOS","authors":"Lucas Moura Santana;Ewout Martens;Jorge Lagos;Piet Wambacq;Jan Craninckx","doi":"10.1109/OJSSCS.2024.3520525","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3520525","url":null,"abstract":"This work presents a \u0000<inline-formula> <tex-math>$2times $ </tex-math></inline-formula>\u0000 time-interleaved (TI) delta-sigma modulator (DSM) analog-to-digital converter (ADC) leveraging a 6-b noise-coupled (NC) noise-shaping (NS) SAR quantizer. A novel technique to implement the noise coupling mid-quantization is presented to relax the timing bottleneck by parallelizing the operations needed for coupling. The loop filter is implemented using power-efficient, no hold-phase ring amplifiers, with an input capacitor reset presampling to reduce kickback noise in the input network. The complete ADC clocks at a sampling rate of 1.4 GS/s, which is one of the highest among all discrete-time (DT) DSM ADCs and TI NS ADCs to date, and achieves 67/72-dB SNDR/SNR over a 70-MHz bandwidth while consuming 32 mW.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"11-20"},"PeriodicalIF":0.0,"publicationDate":"2024-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10807254","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-17DOI: 10.1109/OJSSCS.2024.3519486
Mingyang Gu;Yunsong Tao;Yi Zhong;Lu Jie;Nan Sun
Time-interleaved (TI) analog-to-digital converters (ADCs) are a widely used architecture in high-speed ADCs. With the growing demand for higher sampling rates, time interleaving plays an increasingly important role. However, imperfections introduced by time interleaving, particularly timing skew, significantly limit the ADC performance. This article presents a comprehensive review of timing skew and its calibration techniques in TI ADCs. It covers the fundamentals of time interleaving, the principle of timing skew, and general considerations of timing-skew calibration. Moreover, it categorizes existing calibration techniques into three types: 1) autocorrelation-based; 2) reference-channel-based; and 3) reference-signal-based, and provides detailed analyses.
{"title":"Timing-Skew Calibration Techniques in Time-Interleaved ADCs","authors":"Mingyang Gu;Yunsong Tao;Yi Zhong;Lu Jie;Nan Sun","doi":"10.1109/OJSSCS.2024.3519486","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3519486","url":null,"abstract":"Time-interleaved (TI) analog-to-digital converters (ADCs) are a widely used architecture in high-speed ADCs. With the growing demand for higher sampling rates, time interleaving plays an increasingly important role. However, imperfections introduced by time interleaving, particularly timing skew, significantly limit the ADC performance. This article presents a comprehensive review of timing skew and its calibration techniques in TI ADCs. It covers the fundamentals of time interleaving, the principle of timing skew, and general considerations of timing-skew calibration. Moreover, it categorizes existing calibration techniques into three types: 1) autocorrelation-based; 2) reference-channel-based; and 3) reference-signal-based, and provides detailed analyses.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"5 ","pages":"1-10"},"PeriodicalIF":0.0,"publicationDate":"2024-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10804623","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143105530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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