Area-Time-Efficient Secure Comb Scalar Multiplication Architecture Based on Recoding.

IF 3 3区 工程技术 Q2 CHEMISTRY, ANALYTICAL Micromachines Pub Date : 2024-10-07 DOI:10.3390/mi15101238
Zhantao Zhang, Weijiang Wang, Jingqi Zhang, Xiang He, Mingzhi Ma, Shiwei Ren, Hua Dang
{"title":"Area-Time-Efficient Secure Comb Scalar Multiplication Architecture Based on Recoding.","authors":"Zhantao Zhang, Weijiang Wang, Jingqi Zhang, Xiang He, Mingzhi Ma, Shiwei Ren, Hua Dang","doi":"10.3390/mi15101238","DOIUrl":null,"url":null,"abstract":"<p><p>With the development of mobile communication, digital signatures with low latency, low area, and high security are in increasing demand. Elliptic curve cryptography (ECC) is widely used because of its security and lightweight. Elliptic curve scalar multiplication (ECSM) is the basic arithmetic in ECC. Based on this background information, we propose our own research objectives. In this paper, a low-latency and low-area ECSM architecture based on the comb algorithm is proposed. The detailed methodology is as follows. The recoding-k algorithm and randomization-Z algorithm are used to improve security, which can resist sample power analysis (SPA) and differential power analysis (DPA). A low-area multi-functional architecture for comb is proposed, which takes into account different stages of the comb algorithm. Based on this, the data dependency is considered and the comb architecture is optimized to achieve a uniform and efficient execution pattern. The interleaved modular multiplication algorithm and modified binary inverse algorithm are used to achieve short clock cycle delay and high frequency while taking into account the need for a low area. The proposed architecture has been implemented on Xilinx Virtex-7 series FPGA to perform ECSM on 256-bits prime field GF(p). In the hardware architecture with only 7351 slices of resource usage, a single ECSM only takes 0.74 ms, resulting in an area-time product (ATP) of 5.41. The implementation results show that our design can compete with the existing state-of-the-art engineering in terms of performance and has higher security. Our design is suitable for computing scenarios where security and computing speed are required. The implementation of the overall architecture is of great significance and inspiration to the research community.</p>","PeriodicalId":18508,"journal":{"name":"Micromachines","volume":"15 10","pages":""},"PeriodicalIF":3.0000,"publicationDate":"2024-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.ncbi.nlm.nih.gov/pmc/articles/PMC11509111/pdf/","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Micromachines","FirstCategoryId":"5","ListUrlMain":"https://doi.org/10.3390/mi15101238","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"CHEMISTRY, ANALYTICAL","Score":null,"Total":0}
引用次数: 0

Abstract

With the development of mobile communication, digital signatures with low latency, low area, and high security are in increasing demand. Elliptic curve cryptography (ECC) is widely used because of its security and lightweight. Elliptic curve scalar multiplication (ECSM) is the basic arithmetic in ECC. Based on this background information, we propose our own research objectives. In this paper, a low-latency and low-area ECSM architecture based on the comb algorithm is proposed. The detailed methodology is as follows. The recoding-k algorithm and randomization-Z algorithm are used to improve security, which can resist sample power analysis (SPA) and differential power analysis (DPA). A low-area multi-functional architecture for comb is proposed, which takes into account different stages of the comb algorithm. Based on this, the data dependency is considered and the comb architecture is optimized to achieve a uniform and efficient execution pattern. The interleaved modular multiplication algorithm and modified binary inverse algorithm are used to achieve short clock cycle delay and high frequency while taking into account the need for a low area. The proposed architecture has been implemented on Xilinx Virtex-7 series FPGA to perform ECSM on 256-bits prime field GF(p). In the hardware architecture with only 7351 slices of resource usage, a single ECSM only takes 0.74 ms, resulting in an area-time product (ATP) of 5.41. The implementation results show that our design can compete with the existing state-of-the-art engineering in terms of performance and has higher security. Our design is suitable for computing scenarios where security and computing speed are required. The implementation of the overall architecture is of great significance and inspiration to the research community.

查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
基于重编码的面积-时间高效安全组合标量乘法体系结构。
随着移动通信的发展,对低延迟、低面积和高安全性的数字签名的需求越来越大。椭圆曲线加密算法(ECC)因其安全性和轻便性而得到广泛应用。椭圆曲线标量乘法(ECSM)是 ECC 的基本运算。基于这些背景信息,我们提出了自己的研究目标。本文提出了一种基于梳状算法的低延迟、低面积 ECSM 架构。具体方法如下。采用重新编码-k 算法和随机化-Z 算法提高安全性,可抵御采样功率分析(SPA)和差分功率分析(DPA)。考虑到梳理算法的不同阶段,提出了梳理的低面积多功能架构。在此基础上,考虑了数据依赖性,优化了梳齿架构,以实现统一高效的执行模式。采用交错模块乘法算法和改进的二进制逆算法,以实现较短的时钟周期延迟和较高的频率,同时兼顾低面积需求。所提出的架构已在 Xilinx Virtex-7 系列 FPGA 上实现,可在 256 位素数域 GF(p) 上执行 ECSM。在仅占用 7351 片资源的硬件架构中,单次 ECSM 仅需 0.74 毫秒,面积-时间乘积(ATP)为 5.41。实现结果表明,我们的设计在性能上可以与现有的先进工程相媲美,并且具有更高的安全性。我们的设计适用于对安全性和计算速度有要求的计算场景。整体架构的实现对研究界具有重要意义和启发。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
Micromachines
Micromachines NANOSCIENCE & NANOTECHNOLOGY-INSTRUMENTS & INSTRUMENTATION
CiteScore
5.20
自引率
14.70%
发文量
1862
审稿时长
16.31 days
期刊介绍: Micromachines (ISSN 2072-666X) is an international, peer-reviewed open access journal which provides an advanced forum for studies related to micro-scaled machines and micromachinery. It publishes reviews, regular research papers and short communications. Our aim is to encourage scientists to publish their experimental and theoretical results in as much detail as possible. There is no restriction on the length of the papers. The full experimental details must be provided so that the results can be reproduced.
期刊最新文献
A Sub-1 ppm/°C Reference Voltage Source with a Wide Input Range. A Thorough Review of Emerging Technologies in Micro- and Nanochannel Fabrication: Limitations, Applications, and Comparison. Integration of Metrology in Grinding and Polishing Processes for Rotationally Symmetrical Aspherical Surfaces with Optimized Material Removal Functions. Investigation on the Machinability of Polycrystalline ZnS by Micro-Laser-Assisted Diamond Cutting. Optimal Control of FSBB Converter with Aquila Optimizer-Based PID Controller.
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1